csl_dspchal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... DSPC - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_dspchal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for DSPC:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for DSPC HPIBCTL register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _DSPC_HPIBCTL_GET()			_REG_GET(_DSPC_HPIBCTL_ADDR)
#define _DSPC_HPIBCTL_SET(Val)			_REG_SET(_DSPC_HPIBCTL_ADDR, Val)
#define _DSPC_HPIBCTL_AOI(AND,OR,INV)		_REG_AOI(_DSPC_HPIBCTL_ADDR,AND,OR,INV)
#define _DSPC_HPIBCTL_FGET(Field)			_FIELD_GET(_DSPC_HPIBCTL_ADDR, _DSPC_HPIBCTL_##Field##)
#define _DSPC_HPIBCTL_FSET(Field, Val)		_FIELD_SET(_DSPC_HPIBCTL_ADDR, _DSPC_HPIBCTL_##Field##, Val)
#define _DSPC_HPIBCTL_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_DSPC_HPIBCTL_ADDR, _DSPC_HPIBCTL_##Field##, AND, OR, INV)

#define _DSPC_HPIBCTL_DBIO_SHIFT		(10)
#define _DSPC_HPIBCTL_DBIO_MK(n)		(((Uint16)(n) & 0x0001u) << _DSPC_HPIBCTL_DBIO_SHIFT)
#define _DSPC_HPIBCTL_DBIO_MASK			(_DSPC_HPIBCTL_DBIO_MK(0x0001u))
#define _DSPC_HPIBCTL_DBIO_CLR			(~(_DSPC_HPIBCTL_DBIO_MASK))

#define _DSPC_HPIBCTL_DHOLD_SHIFT		(9)
#define _DSPC_HPIBCTL_DHOLD_MK(n)		(((Uint16)(n) & 0x0001u) << _DSPC_HPIBCTL_DHOLD_SHIFT)
#define _DSPC_HPIBCTL_DHOLD_MASK			(_DSPC_HPIBCTL_DHOLD_MK(0x0001u))
#define _DSPC_HPIBCTL_DHOLD_CLR			(~(_DSPC_HPIBCTL_DHOLD_MASK))

#define _DSPC_HPIBCTL_DRST_SHIFT		(8)
#define _DSPC_HPIBCTL_DRST_MK(n)		(((Uint16)(n) & 0x0001u) << _DSPC_HPIBCTL_DRST_SHIFT)
#define _DSPC_HPIBCTL_DRST_MASK			(_DSPC_HPIBCTL_DRST_MK(0x0001u))
#define _DSPC_HPIBCTL_DRST_CLR			(~(_DSPC_HPIBCTL_DRST_MASK))

#define _DSPC_HPIBCTL_DINT0_SHIFT		(7)
#define _DSPC_HPIBCTL_DINT0_MK(n)		(((Uint16)(n) & 0x0001u) << _DSPC_HPIBCTL_DINT0_SHIFT)
#define _DSPC_HPIBCTL_DINT0_MASK			(_DSPC_HPIBCTL_DINT0_MK(0x0001u))
#define _DSPC_HPIBCTL_DINT0_CLR			(~(_DSPC_HPIBCTL_DINT0_MASK))

#define _DSPC_HPIBCTL_EXCHG_SHIFT		(5)
#define _DSPC_HPIBCTL_EXCHG_MK(n)		(((Uint16)(n) & 0x0001u) << _DSPC_HPIBCTL_EXCHG_SHIFT)
#define _DSPC_HPIBCTL_EXCHG_MASK			(_DSPC_HPIBCTL_EXCHG_MK(0x0001u))
#define _DSPC_HPIBCTL_EXCHG_CLR			(~(_DSPC_HPIBCTL_EXCHG_MASK))

#define _DSPC_HPIBCTL_HPNMI_SHIFT		(3)
#define _DSPC_HPIBCTL_HPNMI_MK(n)		(((Uint16)(n) & 0x0001u) << _DSPC_HPIBCTL_HPNMI_SHIFT)
#define _DSPC_HPIBCTL_HPNMI_MASK			(_DSPC_HPIBCTL_HPNMI_MK(0x0001u))
#define _DSPC_HPIBCTL_HPNMI_CLR			(~(_DSPC_HPIBCTL_HPNMI_MASK))

#define _DSPC_HPIBCTL_HPIEN_SHIFT		(0)
#define _DSPC_HPIBCTL_HPIEN_MK(n)		((Uint16)(n) & 0x0001u) 
#define _DSPC_HPIBCTL_HPIEN_MASK			(_DSPC_HPIBCTL_HPIEN_MK(0x0001u))
#define _DSPC_HPIBCTL_HPIEN_CLR			(~(_DSPC_HPIBCTL_HPIEN_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for DSPC HPIBSTAT register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _DSPC_HPIBSTAT_GET()			_REG_GET(_DSPC_HPIBSTAT_ADDR)
#define _DSPC_HPIBSTAT_SET(Val)			_REG_SET(_DSPC_HPIBSTAT_ADDR, Val)
#define _DSPC_HPIBSTAT_AOI(AND,OR,INV)		_REG_AOI(_DSPC_HPIBSTAT_ADDR,AND,OR,INV)
#define _DSPC_HPIBSTAT_FGET(Field)			_FIELD_GET(_DSPC_HPIBSTAT_ADDR, _DSPC_HPIBSTAT_##Field##)
#define _DSPC_HPIBSTAT_FSET(Field, Val)		_FIELD_SET(_DSPC_HPIBSTAT_ADDR, _DSPC_HPIBSTAT_##Field##, Val)
#define _DSPC_HPIBSTAT_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_DSPC_HPIBSTAT_ADDR, _DSPC_HPIBSTAT_##Field##, AND, OR, INV)

#define _DSPC_HPIBSTAT_DXF_SHIFT		(12)
#define _DSPC_HPIBSTAT_DXF_MK(n)		(((Uint16)(n) & 0x0001u) << _DSPC_HPIBSTAT_DXF_SHIFT)
#define _DSPC_HPIBSTAT_DXF_MASK			(_DSPC_HPIBSTAT_DXF_MK(0x0001u))
#define _DSPC_HPIBSTAT_DXF_CLR			(~(_DSPC_HPIBSTAT_DXF_MASK))

#define _DSPC_HPIBSTAT_HOLDA_SHIFT		(8)
#define _DSPC_HPIBSTAT_HOLDA_MK(n)		(((Uint16)(n) & 0x0001u) << _DSPC_HPIBSTAT_HOLDA_SHIFT)
#define _DSPC_HPIBSTAT_HOLDA_MASK			(_DSPC_HPIBSTAT_HOLDA_MK(0x0001u))
#define _DSPC_HPIBSTAT_HOLDA_CLR			(~(_DSPC_HPIBSTAT_HOLDA_MASK))

#define _DSPC_HPIBSTAT_HINT_SHIFT		(0)
#define _DSPC_HPIBSTAT_HINT_MK(n)		((Uint16)(n) & 0x0001u) 
#define _DSPC_HPIBSTAT_HINT_MASK			(_DSPC_HPIBSTAT_HINT_MK(0x0001u))
#define _DSPC_HPIBSTAT_HINT_CLR			(~(_DSPC_HPIBSTAT_HINT_MASK))