sagiters.c

dm270 source code

/*
Module Name	: sagiters.c

Functions	: SAGITERSInit

Author		: Otis	Yu	

Purpose		: Initializes peripheral device

Notes		: 

*/

/*--------------------------------------------------------------------------*
*	Local header files						 							    *
*--------------------------------------------------------------------------*/
#include <demo/sagiters.h>

/*--------------------------------------------------------------------------*
*	Const, Macro, type definition					 					    *
*--------------------------------------------------------------------------*/
#define REG             *(unsigned short*)

/* SDRAM Controllor */
#define SDMODE			0x309A6
#define REFCTL			0x309A8

/* SAMSUNG K4S281632e setting */
#define TRDL            1
#define SDRAM_BIT_WD	0           // 32-bit SDRAM
#define CAS_LAT         1           // cas latency 2:2 cycle, 1:1 cycle
#define BANK_NUM        1           // back number 0:2 bank, 1:4 bank
#define MEM_TYPE        2           // memory type 0:2k*256, 1:4k*256,
                                    //             2:4K*512, 3:8k*512
#define REF_EN          1           // refresh enable 0:disable, 1:enable
#define REF_CYCLE       0x40        // refresh cycle (REFNUM)
#define DMA_SELECT1     0           // External Memory I/F <-> SDRAM
#define DMA_SELECT2     4           // Serial I/F          <-> SDRAM
#define MRS             0x01        // mode register set
#define PREA            0x02        // precharge all
#define REF             0x04        // auto refresh

/*Clock Controllor */
#define	PLLA			0x30880
#define	PLLB			0x30882
#define	CLKC			0x30884
#define	SEL				0x30886
#define	DIV				0x30888
#define	BYP				0x3088A
#define	MOD0			0x30890
#define	MOD1			0x30892
#define	MOD2			0x30894

/* External Memory Interface */
#define DPSTR0      0x30A4A //FLASH end address in units of 1 MB
#define DPSTR1      0x30A4C //SDRAM end address in units of 1 MB
#define DPSTR2      0x30A4E //CF end address in units of 1 MB
#define DPSTR3      0x30A50
#define DPSTR4      0x30A52
#define DPSTR5      0x30A54


/*---------------------------------------------------------*
*	Brief		:	SDRAMCInit
*	Return		:	
*	Description :						
*----------------------------------------------------------*/
SDRAMCInit()
{
    unsigned short nMode;
    unsigned short refctl_value;
    int i;

    // set SDRAM mode
    nMode = (TRDL << 15) | (SDRAM_BIT_WD << 14) | (CAS_LAT << 10) | (BANK_NUM << 12)  | (MEM_TYPE << 8);
	refctl_value =	(DMA_SELECT1 << 13) | (DMA_SELECT2 << 10) | (REF_EN << 8) | (REF_CYCLE) ;

    REG SDMODE = nMode;
    REG REFCTL = refctl_value ;
    REG SDMODE = nMode | PREA;      // precharge
    for (i = 0; i < 8; i++) 
    {
        REG SDMODE = nMode | REF;   // auto refresh 8 times
    }

    REG SDMODE = nMode | MRS;       // mode register set
    REG SDMODE = (nMode &= ~0xbf);
}

/*---------------------------------------------------------*
*	Brief		:	CLOCKCInit
*	Return		:	
*	Description :						
*----------------------------------------------------------*/
CLOCKCInit()
{
    unsigned long   buf0, buf1;
    
#define PLLA_PMA_DIV	9		//PLLAOUT = 27 * PLLA_PMA_DIV / PLLA_PNA_DIV 
#define PLLA_PNA_DIV	1        //        =  27 * 9 / 1 = 243 MHz
#define PLLB_PMA_DIV	15        //PLLBOUT = 27 * PLLB_PMA_DIV / PLLB_PNA_DIV 
#define PLLB_PNA_DIV	2        //        =  27 * 9 / 1 = 243 MHz          
                                            
#define ARM_CLK_DIV		2        //ARM_CLK = PLLA(B)OUT / ARM_CLK_DIV         
									//		  = 243 / 4 = 60.75 MHz
#define DSP_CLK_DIV		2        //DSP_CLK = PLLA(B)OUT / DSP_CLK_DIV         
									//		  = 243 / 3 = 81 MHz
#define SDR_CLK_DIV		2        //SDR_CLK = PLLA(B)OUT / SDR_CLK_DIV         
									//		  = 243 / 3 = 81 MHz
#define AXL_CLK_DIV		1        //AXL_CLK = PLLA(B)OUT / AXL_CLK_DIV 
									//		  = 243 / 3 = 81 MHz
#define CLK_SEL			0x1001		//AXL = A , SDR = B , DSP = A , ARM = A

#define PLLA_OUT_DIV	((PLLA_PMA_DIV - 1) << 4) | (PLLA_PNA_DIV - 1)
#define PLLB_OUT_DIV	((PLLB_PMA_DIV - 1) << 4) | (PLLB_PNA_DIV - 1)
#define DIV_VALUE		(ARM_CLK_DIV - 1) | ((DSP_CLK_DIV - 1) << 4) | ((SDR_CLK_DIV - 1) << 8) | ((AXL_CLK_DIV - 1) << 12)

	/**************/
	/* PLL BYPASS */
	/**************/
	REG	BYP		= 0x1111;				// Bypass Enable

    /***********************/
    /* Select Source Clock */
    /***********************/
    REG CLKC    = 0x23e8;

    /**********************************/
    /* Set PLL A & B */
    /**********************************/
    REG PLLA    = PLLA_OUT_DIV;
    REG PLLB    = PLLB_OUT_DIV;

    REG SEL     = CLK_SEL;
 
    /*********************/
    /* Set PLL DIV Value */
    /*********************/
    REG DIV     = DIV_VALUE;                            

	/****************************************/
	/* Lock Monitor for PLLA, PLLB and PLLC */
	/****************************************/
	do {
		buf0	= REG PLLA & 0x8000;	// Lock Monitor for PLLA
		buf1	= REG PLLB & 0x8000;	// Lock Monitor for PLLB
	} while(!buf0 || !buf1);	// If ALL PLL's Lock ON then pass.

	/**************/
	/* PLL BYPASS */
	/**************/
	REG	BYP		= 0x0000;				// Bypass Disable

	/*******************************/
	/* All peripheral Clock Enable */
	/*******************************/
	REG CLKC	= 0x23e8;
	REG MOD0 	= 0xffff;
	REG MOD1 	= 0xffff;
    REG MOD2    = 0xffff;
}

/*---------------------------------------------------------*
*	Brief		:	EMIFInit
*	Return		:	
*	Description :						
*----------------------------------------------------------*/
EMIFInit()
{
/* make sure the following addresses do not overlap */
#define EMIF0_END_ADDRESS       0x09    // in 1MB unit
#define EMIF_SDRAM_END_ADDRESS  0x49
#define EMIF1_END_ADDRESS       0x61
#define EMIF2_END_ADDRESS       0x79
#define EMIF3_END_ADDRESS       0x91
#define EMIF4_END_ADDRESS       0xa9
    //memory map
    REG DPSTR0 = EMIF0_END_ADDRESS;
    REG DPSTR1 = EMIF_SDRAM_END_ADDRESS;
    REG DPSTR2 = EMIF1_END_ADDRESS;
    REG DPSTR3 = EMIF2_END_ADDRESS;
}

/*--------------------------------------------------------------------------*
*	Brief		:	SAGITERSInit		 									*
*	Return		:	None													*
*	Description	:															*
*--------------------------------------------------------------------------*/
void SAGITERSInit(void) {
	
	CLKCInit();
	EMIFInit();
    GIOInit();
    INTCInit();
    UARTInit();
    OSDInit();
    DEV_LCM_Init();		/* LCMUPS051 init */
    //HIMAX8802Init();
	//M41T81_Init();
	//AIC23_Init();
	VENC_enable(TRUE);
	CLKC_m48xiEnable(TRUE);
    CLKC_m48xiEnable(FALSE);
}