clock_test.c

dm270 source code

/*
Module Name	: clock_test.c

Functions	: CLOCK_TEST
			  CLOCK_COMPARE
			  REVISION_TEST
    
Purpose		: Test DM270 frequency and show revision

Notes		: 
This function is setting and compare frequency for arm, dsp, sdram and axl;
Show DM270 revision.
*/

// Local header files
#include <demo/uart270.h>
#include <demo/clkc270.h>

// Extern global variables
extern char UART_outBuff[1024];

// Forward declarations of functions included
void REVISION_TEST(void);
void CLOCK_TEST(void);
void CLOCK_COMPARE(CLKC_ConfigData *clkcConfig);

static const CLKC_ConfigData clkcConfig1 = {
    9,				// PLLA_M1;
    1,				// PLLA_N1;
    15,				// PLLB_M1;
    2,				// PLLB_N1;

	CLKC_PLLB_OUT,	// SELAXL;
	CLKC_PLLA_OUT,	// SELSDRC;
	CLKC_PLLB_OUT,	// SELARM;
	CLKC_PLLA_OUT,	// SELDSP;

	3,				// DIVAXL;
	4,				// DIVSDRC;
	4,				// DIVARM;
	4				// DIVDSP;
};

static const CLKC_ConfigData clkcConfig2 = {
    11,				// PLLA_M1;
    3,				// PLLA_N1;
    13,				// PLLB_M1;
    2,				// PLLB_N1;

	CLKC_PLLB_OUT,	// SELAXL;
	CLKC_PLLA_OUT,	// SELSDRC;
	CLKC_PLLB_OUT,	// SELARM;
	CLKC_PLLA_OUT,	// SELDSP;

	1,				// DIVAXL;
	1,				// DIVSDRC;
	2,				// DIVARM;
	1				// DIVDSP;
};

static const CLKC_ConfigData clkcConfig3 = {
    15,				// PLLA_M1;
    2,				// PLLA_N1;
    9,				// PLLB_M1;
    1,				// PLLB_N1;

	CLKC_PLLA_OUT,	// SELAXL;
	CLKC_PLLB_OUT,	// SELSDRC;
	CLKC_PLLA_OUT,	// SELARM;
	CLKC_PLLB_OUT,	// SELDSP;

	1,				// DIVAXL;
	2,				// DIVSDRC;
	2,				// DIVARM;
	2				// DIVDSP;
};

struct {
    unsigned int arm;
    unsigned int dsp;
    unsigned int sdram;
    unsigned int axl;
    
    unsigned int reg_arm;
    unsigned int reg_dsp;
    unsigned int reg_sdram;
    unsigned int reg_axl;
} Clock_Check;

//
// Test arm, dsp, sdram and axl frequency

void CLOCK_TEST(void) {
	UART_sendString( UART0, "\r\n ***************CLOCK  TEST***************" );
	
	CLKC_setConfig((CLKC_ConfigData*)&clkcConfig1);
	CLOCK_COMPARE((CLKC_ConfigData*)&clkcConfig1);
	UART_sendString( UART0,  "\r\n " );
	
	CLKC_setConfig((CLKC_ConfigData*)&clkcConfig2);
	CLOCK_COMPARE((CLKC_ConfigData*)&clkcConfig2);
	UART_sendString( UART0,  "\r\n " );
	
	CLKC_setConfig((CLKC_ConfigData*)&clkcConfig3);
	CLOCK_COMPARE((CLKC_ConfigData*)&clkcConfig3);
	UART_sendString( UART0,  "\r\n " );
}

//
// Compare arm, dsp, sdram and axl frequency

void CLOCK_COMPARE(CLKC_ConfigData *clkcConfig) {
	unsigned int value;
	
	if(clkcConfig == 0) {
		UART_sendString( UART0,  "\r\n Compare ERROR " );
	}
        
	value = 27*1000*1000;
// ARM
	if( clkcConfig->armPll == 0 ) {
		Clock_Check.reg_arm = (value*clkcConfig->pllA_M)/clkcConfig->pllA_N;
	} else {
		Clock_Check.reg_arm = (value*clkcConfig->pllB_M)/clkcConfig->pllB_N;
	}
	Clock_Check.reg_arm /= clkcConfig->armDiv;
// DSP	
	if( clkcConfig->dspPll == 0 ) {
		Clock_Check.reg_dsp = (value*clkcConfig->pllA_M)/clkcConfig->pllA_N;
	} else {
		Clock_Check.reg_dsp = (value*clkcConfig->pllB_M)/clkcConfig->pllB_N;
	}
	Clock_Check.reg_dsp /= clkcConfig->dspDiv;
// SDRAM
	if( clkcConfig->sdramPll == 0 ) {
		Clock_Check.reg_sdram = (value*clkcConfig->pllA_M)/clkcConfig->pllA_N;
	} else {
		Clock_Check.reg_sdram = (value*clkcConfig->pllB_M)/clkcConfig->pllB_N;
	}
	Clock_Check.reg_sdram /= clkcConfig->sdramDiv;
// AXL
	if( clkcConfig->axlPll == 0 ) {
		Clock_Check.reg_axl = (value*clkcConfig->pllA_M)/clkcConfig->pllA_N;
	} else {
		Clock_Check.reg_axl = (value*clkcConfig->pllB_M)/clkcConfig->pllB_N;
	}
	Clock_Check.reg_axl /= clkcConfig->axlDiv;
	
	Clock_Check.arm   = CLKC_getClockValue( CLK_ARM );
	Clock_Check.dsp   = CLKC_getClockValue( CLK_DSP );
	Clock_Check.sdram = CLKC_getClockValue( CLK_SDRC );
	Clock_Check.axl   = CLKC_getClockValue( CLK_AXL );	
	
	sprintf(UART_outBuff, "\r\n CHECK ARM CLK   = %4d.%-6ld MHz", Clock_Check.reg_arm/1000000, Clock_Check.reg_arm%1000000);
	UART_sendString( UART0,  UART_outBuff );
	if( Clock_Check.reg_arm != Clock_Check.arm ) {
		UART_sendString( UART0,  "\r\n ERROR " );
	}
	
	sprintf(UART_outBuff, "\r\n CHECK DSP CLK   = %4d.%-6ld MHz", Clock_Check.reg_dsp/1000000, Clock_Check.reg_dsp%1000000);
	UART_sendString( UART0,  UART_outBuff );
	if( Clock_Check.reg_dsp != Clock_Check.dsp ) {
		UART_sendString( UART0,  "\r\n ERROR " );
	}
	
	sprintf(UART_outBuff, "\r\n CHECK SDRAM CLK = %4d.%-6ld MHz", Clock_Check.reg_sdram/1000000, Clock_Check.reg_sdram%1000000);
	UART_sendString( UART0,  UART_outBuff );
	if( Clock_Check.reg_sdram != Clock_Check.sdram ) {
		UART_sendString( UART0,  "\r\n ERROR " );
	}
	
	sprintf(UART_outBuff, "\r\n CHECK AXL CLK   = %4d.%-6ld MHz", Clock_Check.reg_axl/1000000, Clock_Check.reg_axl%1000000);
	UART_sendString( UART0,  UART_outBuff );
	if( Clock_Check.reg_axl != Clock_Check.axl ) {
		UART_sendString( UART0,  "\r\n ERROR " );
	}
	
	if(( Clock_Check.reg_axl == Clock_Check.axl ) && ( Clock_Check.reg_sdram == Clock_Check.sdram ) &&
	   ( Clock_Check.reg_dsp == Clock_Check.dsp ) && ( Clock_Check.reg_arm == Clock_Check.arm )) {
		UART_sendString( UART0,  "\r\n PASS " );
	}
	
}

//
// Show DM270 revision

void REVISION_TEST(void) {
	unsigned char  revID;
	
	revID = BUSC_getDeviceRevision();
	sprintf( UART_outBuff, "\r\n *** Silicon Revision : DM270 ES%d.%d ***", revID>>4, revID&0xF );
	UART_sendString( UART0,  UART_outBuff );

	UART_sendString( UART0,  "\r\n " );
		
}