extmem.c

dm270 source code

#include <user/extmem.h>
//#include "..\system\iodef.h"


/* External Memory Interface Register Define */
#define	CS0CTRL1		0x30A00
#define	CS3CTRL1		0x30A0E
#define	CS4CTRL1		0x30A12
#define	CS1CTRL1A		0x30A04
#define	CS1CTRL1B		0x30A06
#define	CS2CTRL1		0x30A0A
#define	CS0CTRL2		0x30A02
#define	CS1CTRL2		0x30A08
#define	CS2CTRL2		0x30A0C
#define	CS3CTRL2		0x30A10
#define	CS4CTRL2		0x30A14
#define	BUSCTRL			0x30A16
#define	BUSRLS			0x30A18
#define	CFCTRL1			0x30A1A
#define	CFCTRL2			0x30A1C
#define	SMCTRL			0x30A1E
#define	BUSINTEN		0x30A20
#define	BUSINTSTS		0x30A22
#define	BUSSTS			0x30A24
#define	BUSWAITMD		0x30A26
#define	ECC1CP			0x30A28
#define	ECC1LP			0x30A2A
#define	ECC2CP			0x30A2C
#define	ECC2LP			0x30A2E
#define	ECCCLR			0x30A30
#define	PAGESZ			0x30A32
#define	VIFCDSPDEST		0x30A34
#define	PRIORCTL		0x30A36
#define	SURCEADD1		0x30A38
#define	SURCEADD2		0x30A3A
#define	DESTADD1		0x30A3C
#define	DESTADD2		0x30A3E
#define	DMASIZE			0x30A40
#define	DMADEVSEL		0x30A42
#define	EMIFDMACTL		0x30A44
#define	VIFCDSPADD1		0x30A46
#define	VIFCDSPADD2		0x30A48
#define	DPSTR0			0x30A4A
#define	DPSTR1			0x30A4C
#define	DPSTR2			0x30A4E
#define	DPSTR3			0x30A50
#define	DPSTR4			0x30A52
#define	DPSTR5			0x30A54
#define	EMIF_TEST		0x30A56
struct EXMEM *s_pMem= (struct EXMEM *)EXMEM_REG_BASE;

void busc_ini(void)
{
    /*
    **  cs1ctrl2:
    **  Number of Clocks of Chip Enable Setup is 0 (bits 0-3)
    **  Number of Clocks of Write Enable Setup is 4 (bits 4-7)
    **  Number of Clocks of Output Enable Setup is 4 (bits 8-11)
    **  Number of IDLE State Clocks is 1 (bits 12-13)
    */
//    s_pMem->cs1ctrl2 = 0x1440;
	*((unsigned short*)CS1CTRL2) = 0x1440;

    /*
    **  cs1ctrl1a:
    **  Cycle width is 14 ARM cycles (bits 0-4)
    **  Chip enable width is 13 ARM cycles (bits 8-12)
    */
//  s_pMem->cs1ctrl1a = 0x0c0d;
	*((unsigned short*)CS1CTRL1A) = 0x0c0d;
    /*
    **  cs1ctrl1b:
    **  Write Enable Width is 9 ARM cycles (bits 0-4)
    **  Output Enable Width is 6 ARM cycles (bits 8-12)
    */
//   g_pMem->cs1ctrl1b = 0x0508;
    *((unsigned short*)CS1CTRL1B) = 0x0508;

    /* Set up for 16-bit bus size  */
//    s_pMem->cfctrl2 = 0x0000;
//    s_pMem->cfctrl1 = 0x0000;
    *((unsigned short*)CFCTRL1) = 0x0000;
    *((unsigned short*)CFCTRL2) = 0x0000;

    /* Set up external memory boundary areas */
//	s_pMem->dpstr0 = 0x09;
//  s_pMem->dpstr1 = 0x49;
//	s_pMem->dpstr2 = 0x61;
//	s_pMem->dpstr3 = 0x79;
//	s_pMem->dpstr4 = 0x91;
//	s_pMem->dpstr5 = 0xA9;
	
	*((unsigned short*)DPSTR0) = 0x09;
    *((unsigned short*)DPSTR1) = 0x29;
	*((unsigned short*)DPSTR2) = 0x61;
	*((unsigned short*)DPSTR3) = 0x79;
	*((unsigned short*)DPSTR4) = 0x91;
	*((unsigned short*)DPSTR5) = 0xA9;
}