clkc.c

dm270 source code

/**
	\file clkc.c
	\brief Clock controller user APIs
*/

#include <system/clkc270.h>

static const CLKC_ConfigData clkcConfig = {
    15,			// pllA_M;
    2,			// pllA_N;
    13,			// pllB_M;
    2,			// pllB_N;

	CLKC_PLLB_OUT,	// axlPll;
	CLKC_PLLA_OUT,	// sdramPll;
	CLKC_PLLB_OUT,	// armPll;
	CLKC_PLLB_OUT,	// dspPll;

	1,			// axlDiv;
	2,			// sdramDiv;
	2,			// armDiv;
	2			// dspDiv;

};

/**
	\brief Initialize ARM, DSP, SDRAM, AXL clock PLLs

	Also enables all CLKC modules \n
	The clock values set by default are as follows:

	\code
	PLLA OUT = PPL IN * M / N = (27Mhz * 13) / 2
	PLLB OUT = PPL IN * M / N = (27Mhz * 14) / 2

	AXL   CLK  = PPLB OUT / 1 = 175.5  Mhz
	SDRAM CLK  = PPLA OUT / 2 =  81    Mhz
	ARM   CLK  = PPLB OUT / 2 =  87.75 Mhz
	DSP   CLK  = PPLB OUT / 2 =  87.75 Mhz
	
	\endcode

	See clkc.c file to change default clock values

	\return if success E_PASS, else error code
*/
STATUS CLKCInit() {
	STATUS status=E_PASS;

	status = CLKC_setConfig( (CLKC_ConfigData*)&clkcConfig );

	CLKC_moduleEnableAll();

	return status;
}