📄 wm8750.c

📁 dm270 source code
💻 C
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			case	44118:
				DEV_ADEC_SampleRate_SR(0x11);
				DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
				break;

			case	441188021:
				DEV_ADEC_SampleRate_SR(0x13);
				DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
				break;

			case	48000:
				DEV_ADEC_SampleRate_SR(0x00);
				DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
				break;

			case	480008000:
				DEV_ADEC_SampleRate_SR(0x02);
				DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
				break;

			case	88235:
				DEV_ADEC_SampleRate_SR(0x1F);
				DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
				break;

			case	96000:
				DEV_ADEC_SampleRate_SR(0x0E);
				DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
				break;
		}
	dev_audio_scsr_usb_end:
	return	ret;
	}
	
	else
	{
		ret = DEV_ADEC_SampleRate_USB(FALSE);
		if( ret != E_PASS )	goto	dev_audio_scsr_end;
		
		if(Oscillator_Freq == 24576000)
		{
			Oscillator_Freq = 12288000;
			DEV_ADEC_SampleRate_CLKDIV2(TRUE);
		}
		else if(Oscillator_Freq == 22579200)
		{
			Oscillator_Freq = 11289600;
			DEV_ADEC_SampleRate_CLKDIV2(TRUE);
		}
		else if(Oscillator_Freq == 36864000)
		{
			Oscillator_Freq = 18432000;
			DEV_ADEC_SampleRate_CLKDIV2(TRUE);
		}
		else if(Oscillator_Freq == 33868800)
		{
			Oscillator_Freq = 16934400;
			DEV_ADEC_SampleRate_CLKDIV2(TRUE);
		}
		else
		{
			DEV_ADEC_SampleRate_CLKDIV2(FALSE);
		}

		switch(Oscillator_Freq)
		{
			case	12288000:
				switch(Sampling_Freq)
				{
					case	8000:
						DEV_ADEC_SampleRate_SR(0x06);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	800048000:
						DEV_ADEC_SampleRate_SR(0x04);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	12000:
						DEV_ADEC_SampleRate_SR(0x08);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	16000:
						DEV_ADEC_SampleRate_SR(0x0A);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	24000:
						DEV_ADEC_SampleRate_SR(0x1C);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	32000:
						DEV_ADEC_SampleRate_SR(0x0C);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	48000:
						DEV_ADEC_SampleRate_SR(0x00);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	480008000:
						DEV_ADEC_SampleRate_SR(0x02);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	96000:
						DEV_ADEC_SampleRate_SR(0x0E);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				}
				break;

			case	11289600:
				DEV_ADEC_SampleRate_CLKDIV2(FALSE);
				switch(Sampling_Freq)
				{
					case	8018:
						DEV_ADEC_SampleRate_SR(0x16);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	801844100:
						DEV_ADEC_SampleRate_SR(0x14);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	11025:
						DEV_ADEC_SampleRate_SR(0x18);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	22050:
						DEV_ADEC_SampleRate_SR(0x1A);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	44100:
						DEV_ADEC_SampleRate_SR(0x10);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	441008018:
						DEV_ADEC_SampleRate_SR(0x11);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	88200:
						DEV_ADEC_SampleRate_SR(0x1E);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
				}
				break;

			case	18432000:
				DEV_ADEC_SampleRate_CLKDIV2(FALSE);
				switch(Sampling_Freq)
				{
					case	8000:
						DEV_ADEC_SampleRate_SR(0x07);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	800048000:
						DEV_ADEC_SampleRate_SR(0x05);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	12000:
						DEV_ADEC_SampleRate_SR(0x09);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	16000:
						DEV_ADEC_SampleRate_SR(0x0B);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	24000:
						DEV_ADEC_SampleRate_SR(0x1D);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	32000:
						DEV_ADEC_SampleRate_SR(0x0D);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	48000:
						DEV_ADEC_SampleRate_SR(0x01);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	480008000:
						DEV_ADEC_SampleRate_SR(0x03);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	96000:
						DEV_ADEC_SampleRate_SR(0x0F);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				}
				break;

			case	16934400:
				DEV_ADEC_SampleRate_CLKDIV2(FALSE);
				switch(Sampling_Freq)
				{
					case	8018:
						DEV_ADEC_SampleRate_SR(0x17);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	801844100:
						DEV_ADEC_SampleRate_SR(0x15);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;

					case	11025:
						DEV_ADEC_SampleRate_SR(0x19);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	22050:
						DEV_ADEC_SampleRate_SR(0x1B);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	44100:
						DEV_ADEC_SampleRate_SR(0x11);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	441008018:
						DEV_ADEC_SampleRate_SR(0x13);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
					case	88200:
						DEV_ADEC_SampleRate_SR(0x1F);
						DEV_ADEC_WriteCmd(R8_Sample_Rate, WM8750Regs[8]);
						break;
				
				}
				break;
		}
	dev_audio_scsr_end:
	return	ret;
	}
}

/*--------------------------------------------------------------------------*
*	Brief		:	Audio codec write command								*
*	Return		:	None													*
*	Description	:															*
*--------------------------------------------------------------------------*/
STATUS	DEV_ADEC_WriteCmd( unsigned char Reg, unsigned short Val )
{
	unsigned char dat1, dat2;
	//unsigned short i=0;
	STATUS status=E_PASS;
	
		
	dat1 = Reg << 1;
	dat1 |= !!(Val & 0x0100);
	dat2 = (unsigned char) (Val & 0xFF);
	i2cInit();
	i2cWriteReg((unsigned char)WM8750_I2C_SLAVE, (unsigned char)dat1, (unsigned char)dat2, &success);
		
	if(success)
 	{
		UART_sendString( UART0, "\r\n WM8750L control fail.");
		status=E_INVALID_INPUT;
	}
	//sig_sem(SEMID_I2C);
	return status;
}


/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
/*--------------------------------------------------------------------------*
*	For Driver Control Call													*
*---------------------------------------------------------------------------*
*	Brief		:	Audio codec setting function							*
*	Return		:	None													*
*	Description	:															*
*--------------------------------------------------------------------------*/
/*	Left Channel PGA	*/
STATUS	DEV_ADEC_LeftInputVol_LIVU(BOOL trueorfalse)
{
	if(trueorfalse)	WM8750Regs[0] |=0x0100;
	else			WM8750Regs[0] &=0xFEFF;
	return	DEV_ADEC_WriteCmd(R0_Left_Input_Volume, WM8750Regs[0]);
}
/*-------------------------------------------------------------------------*/
STATUS	DEV_ADEC_LeftInputVol_LINMUTE(BOOL trueorfalse)
{
	if(trueorfalse)	WM8750Regs[0] |=0x0080;
	else			WM8750Regs[0] &=0xFF7F;
	return	DEV_ADEC_WriteCmd(R0_Left_Input_Volume, WM8750Regs[0]);
}
/*-------------------------------------------------------------------------*/
STATUS	DEV_ADEC_LeftInputVol_LIZC(BOOL trueorfalse)
{
	if(trueorfalse)	WM8750Regs[0] |=0x0040;
	else			WM8750Regs[0] &=0xFFBF;
	return	DEV_ADEC_WriteCmd(R0_Left_Input_Volume, WM8750Regs[0]);
}
/*-------------------------------------------------------------------------*/
STATUS	DEV_ADEC_LeftInputVol_LINVOL(unsigned char vol)
{
	USHORT	volume, temp;
	
	volume = (USHORT)(vol& 0x3F);
	temp = WM8750Regs[0];
	temp &= 0xFFC0;
	WM8750Regs[0] = temp + volume;
	return	DEV_ADEC_WriteCmd(R0_Left_Input_Volume, WM8750Regs[0]);
}

/*-------------------------------------------------------------------------*/
/*	Right Channel PGA	*/
STATUS	DEV_ADEC_RightInputVol_RIVU(BOOL trueorfalse)
{
	if(trueorfalse)	WM8750Regs[1] |=0x0100;
	else			WM8750Regs[1] &=0xFEFF;
	return	DEV_ADEC_WriteCmd(R1_Right_Input_Volume, WM8750Regs[1]);
}
/*-------------------------------------------------------------------------*/
STATUS	DEV_ADEC_RightInputVol_RINMUTE(BOOL trueorfalse)
{
	if(trueorfalse)	WM8750Regs[1] |=0x0080;
	else			WM8750Regs[1] &=0xFF7F;
	return	DEV_ADEC_WriteCmd(R1_Right_Input_Volume, WM8750Regs[1]);
}
/*-------------------------------------------------------------------------*/
STATUS	DEV_ADEC_RightInputVol_RIZC(BOOL trueorfalse)
{
	if(trueorfalse)	WM8750Regs[1] |=0x0040;
	else			WM8750Regs[1] &=0xFFBF;
	return	DEV_ADEC_WriteCmd(R1_Right_Input_Volume, WM8750Regs[1]);
}
/*-------------------------------------------------------------------------*/
STATUS	DEV_ADEC_RightInputVol_RINVOL(unsigned char vol)
{
	USHORT	volume, temp;
	
	volume = (USHORT)(vol& 0x3F);
	temp = WM8750Regs[1];
	temp &= 0xFFC0;
	WM8750Regs[1] = temp + volume;
	return	DEV_ADEC_WriteCmd(R1_Right_Input_Volume, WM8750Regs[1]);
}

/*-------------------------------------------------------------------------*/
/*	LOUT1 Volume	*/
STATUS	DEV_ADEC_LOUT1Vol_LO1VU(BOOL trueorfalse)
{
	if(trueorfalse)	WM8750Regs[2] |=0x0100;
	else			WM8750Regs[2] &=0xFEFF;
	return	DEV_ADEC_WriteCmd(R2_LOUT1_Volume, WM8750Regs[2]);
}
/*-------------------------------------------------------------------------*/
STATUS	DEV_ADEC_LOUT1Vol_LO1ZC(BOOL trueorfalse)
{
	if(trueorfalse)	WM8750Regs[2] |=0x0080;
	else			WM8750Regs[2] &=0xFF7F;
	return	DEV_ADEC_WriteCmd(R2_LOUT1_Volume, WM8750Regs[2]);
}
/*-------------------------------------------------------------------------*/
STATUS	DEV_ADEC_LOUT1Vol_LOUT1VOL(int vol)
{
	USHORT	volume, temp;
	
	volume = (USHORT)(vol& 0x7F);
	temp = WM8750Regs[2];
	temp &= 0xFF80;
	WM8750Regs[2] = temp + volume;
	return	DEV_ADEC_WriteCmd(R2_LOUT1_Volume, WM8750Regs[2]);
}

/*-------------------------------------------------------------------------*/
/*	ROUT1 Volume	*/
STATUS	DEV_ADEC_ROUT1Vol_RO1VU(BOOL trueorfalse)
{
	if(trueorfalse)	WM8750Regs[3] |=0x0100;
	else			WM8750Regs[3] &=0xFEFF;
	return	DEV_ADEC_WriteCmd(R3_ROUT1_Volume, WM8750Regs[3]);
}
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