iocontrol.txt

输入输出控制的状态机

module IOcontrol(clk,ce3,GPIO,re,we,addr,reset,Z);
output [2:0] Z;
input  reset,clk,ce3,GPIO,re,we,addr;

parameter Idle=4'b0000,S1=4'b0001,S2=4'b0010,S3=4'b0011,S4=4'b0100,S5=4'b0101,S6=4'b0110,S7=4'b0111,S8=4'b1000;
reg [4:0] present_state,next_state;
reg [2:0] Z;
always@(posedge clk)
begin
   if(reset)
   begin
   next_state<=Idle;
   end
   else
   begin
   next_state<=present_state;
 case(present_state)
Idle: begin
        if(ce3==1) begin next_state<=Idle;Z=3'b0;end
        else begin next_state<=S1;Z=3'b0;end
      end
S1:begin
      if(GPIO!==0&&we==0) begin next_state<=S3;Z=3'b0;end
        if(GPIO==0) begin next_state<=S2;Z=3'b0;end
    end
S2:begin
      if(re==1&&we==1) begin next_state<=S3;Z=3'b0;end
        if(re==0) begin next_state<=S4;Z=3'b1;end
          if(we==0) begin next_state<=S5;Z=3'b010;end
    end
S3:begin
      if(we==1) begin next_state<=Idle;Z=3'b0;end
        if(addr==1) begin next_state<=S6;Z=3'b011;end
          if(addr==0) begin next_state<=S7;Z=3'b100;end
    end
S4:begin
      if(re==1) begin next_state<=S8;Z=3'b0;end
   end
S5:begin
      if(we==1) begin next_state<=S8;Z=3'b0;end
   end
S6:begin
      if(we==1) begin next_state<=S8;Z=3'b0;end
   end
S7:begin
      if(we==1) begin next_state<=S8;Z=3'b0;end
   end
S8:begin
      if(ce3==1) begin next_state<=Idle;Z=3'b0;end
      else begin next_state<=S8;Z=3'b0;end
   end
default: next_state<='bx;
 endcase
end
present_state<=next_state;
end
endmodule