huang.tan.qmsg

东西和南北方向各有一组红、黄、绿灯用于指挥交通

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 5 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "f1 " "Info: Detected ripple clock \"f1\" as buffer" {  } { { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "f1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "f100 " "Info: Detected ripple clock \"f100\" as buffer" {  } { { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 17 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "f100" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register seconds\[2\] register ge_right\[1\] 40.65 MHz 24.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 40.65 MHz between source register \"seconds\[2\]\" and destination register \"ge_right\[1\]\" (period= 24.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.100 ns + Longest register register " "Info: + Longest register to register delay is 20.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seconds\[2\] 1 REG LC6_F10 47 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_F10; Fanout = 47; REG Node = 'seconds\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { seconds[2] } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.400 ns) 2.700 ns lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[1\]~49 2 COMB LC4_F3 2 " "Info: 2: + IC(1.300 ns) + CELL(1.400 ns) = 2.700 ns; Loc. = LC4_F3; Fanout = 2; COMB Node = 'lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[1\]~49'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { seconds[2] lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1]~49 } "NODE_NAME" } } { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/实验三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 4.400 ns lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[2\]~65 3 COMB LC8_F3 2 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 4.400 ns; Loc. = LC8_F3; Fanout = 2; COMB Node = 'lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[2\]~65'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1]~49 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[2]~65 } "NODE_NAME" } } { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/实验三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 6.100 ns lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~57 4 COMB LC2_F3 8 " "Info: 4: + IC(0.300 ns) + CELL(1.400 ns) = 6.100 ns; Loc. = LC2_F3; Fanout = 8; COMB Node = 'lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~57'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[2]~65 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[3]~57 } "NODE_NAME" } } { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/实验三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 8.000 ns lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|StageOut\[17\]~191 5 COMB LC1_F3 2 " "Info: 5: + IC(0.300 ns) + CELL(1.600 ns) = 8.000 ns; Loc. = LC1_F3; Fanout = 2; COMB Node = 'lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|StageOut\[17\]~191'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[3]~57 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|StageOut[17]~191 } "NODE_NAME" } } { "db/alt_u_div_cie.tdf" "" { Text "F:/verilog/实验三操作/huang/db/alt_u_div_cie.tdf" 58 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.600 ns) 10.500 ns lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[3\]~116 6 COMB LC7_F2 1 " "Info: 6: + IC(0.900 ns) + CELL(1.600 ns) = 10.500 ns; Loc. = LC7_F2; Fanout = 1; COMB Node = 'lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[3\]~116'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|StageOut[17]~191 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~116 } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/实验三操作/huang/db/add_sub_n7c.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 12.200 ns lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[4\]~96 7 COMB LC1_F2 3 " "Info: 7: + IC(0.300 ns) + CELL(1.400 ns) = 12.200 ns; Loc. = LC1_F2; Fanout = 3; COMB Node = 'lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[4\]~96'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~116 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~96 } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/实验三操作/huang/db/add_sub_n7c.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 15.000 ns ge_right~4126 8 COMB LC1_F7 1 " "Info: 8: + IC(1.200 ns) + CELL(1.600 ns) = 15.000 ns; Loc. = LC1_F7; Fanout = 1; COMB Node = 'ge_right~4126'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~96 ge_right~4126 } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 16.900 ns ge_right~4127 9 COMB LC2_F7 1 " "Info: 9: + IC(0.300 ns) + CELL(1.600 ns) = 16.900 ns; Loc. = LC2_F7; Fanout = 1; COMB Node = 'ge_right~4127'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ge_right~4126 ge_right~4127 } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 18.800 ns ge_right~4129 10 COMB LC3_F7 1 " "Info: 10: + IC(0.300 ns) + CELL(1.600 ns) = 18.800 ns; Loc. = LC3_F7; Fanout = 1; COMB Node = 'ge_right~4129'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ge_right~4127 ge_right~4129 } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 20.100 ns ge_right\[1\] 11 REG LC4_F7 13 " "Info: 11: + IC(0.300 ns) + CELL(1.000 ns) = 20.100 ns; Loc. = LC4_F7; Fanout = 13; REG Node = 'ge_right\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { ge_right~4129 ge_right[1] } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 188 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.600 ns ( 72.64 % ) " "Info: Total cell delay = 14.600 ns ( 72.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns ( 27.36 % ) " "Info: Total interconnect delay = 5.500 ns ( 27.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "20.100 ns" { seconds[2] lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1]~49 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[2]~65 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[3]~57 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|StageOut[17]~191 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~116 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~96 ge_right~4126 ge_right~4127 ge_right~4129 ge_right[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "20.100 ns" { seconds[2] lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1]~49 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[2]~65 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[3]~57 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|StageOut[17]~191 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~116 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~96 ge_right~4126 ge_right~4127 ge_right~4129 ge_right[1] } { 0.000ns 1.300ns 0.300ns 0.300ns 0.300ns 0.900ns 0.300ns 1.200ns 0.300ns 0.300ns 0.300ns } { 0.000ns 1.400ns 1.400ns 1.400ns 1.600ns 1.600ns 1.400ns 1.600ns 1.600ns 1.600ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.400 ns - Smallest " "Info: - Smallest clock skew is -3.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_79 65 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns ge_right\[1\] 2 REG LC4_F7 13 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_F7; Fanout = 13; REG Node = 'ge_right\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { clk ge_right[1] } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 188 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { clk ge_right[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { clk clk~out ge_right[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.800 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_79 65 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns f1 2 REG LC8_D30 7 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC8_D30; Fanout = 7; REG Node = 'f1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { clk f1 } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.000 ns) 5.800 ns seconds\[2\] 3 REG LC6_F10 47 " "Info: 3: + IC(2.900 ns) + CELL(0.000 ns) = 5.800 ns; Loc. = LC6_F10; Fanout = 47; REG Node = 'seconds\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { f1 seconds[2] } "NODE_NAME" } } { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 43.10 % ) " "Info: Total cell delay = 2.500 ns ( 43.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 56.90 % ) " "Info: Total interconnect delay = 3.300 ns ( 56.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.800 ns" { clk f1 seconds[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.800 ns" { clk clk~out f1 seconds[2] } { 0.000ns 0.000ns 0.400ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { clk ge_right[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { clk clk~out ge_right[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.800 ns" { clk f1 seconds[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.800 ns" { clk clk~out f1 seconds[2] } { 0.000ns 0.000ns 0.400ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 62 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "huang.v" "" { Text "F:/verilog/实验三操作/huang/huang.v" 188 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "20.100 ns" { seconds[2] lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1]~49 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[2]~65 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[3]~57 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|StageOut[17]~191 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~116 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~96 ge_right~4126 ge_right~4127 ge_right~4129 ge_right[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "20.100 ns" { seconds[2] lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1]~49 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[2]~65 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_m7c:add_sub_3|add_sub_cella[3]~57 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|StageOut[17]~191 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~116 lpm_divide:Mod1|lpm_divide_rnl:auto_generated|sign_div_unsign_4kh:divider|alt_u_div_cie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~96 ge_right~4126 ge_right~4127 ge_right~4129 ge_right[1] } { 0.000ns 1.300ns 0.300ns 0.300ns 0.300ns 0.900ns 0.300ns 1.200ns 0.300ns 0.300ns 0.300ns } { 0.000ns 1.400ns 1.400ns 1.400ns 1.600ns 1.600ns 1.400ns 1.600ns 1.600ns 1.600ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { clk ge_right[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { clk clk~out ge_right[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.800 ns" { clk f1 seconds[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.800 ns" { clk clk~out f1 seconds[2] } { 0.000ns 0.000ns 0.400ns 2.900ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}