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📄 huang.vho

📁 东西和南北方向各有一组红、黄、绿灯用于指挥交通
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SIGNAL \ge_right~4131_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4132_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4132_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4133_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4133_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr27~23_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr27~23_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \f100~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \f100~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \g[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \g[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \g[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \g[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector33~3_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector33~3_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \led_seg[0]~reg0_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \led_seg[0]~reg0_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~84_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~84_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_right~822_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_right~822_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_right[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_right[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add6~156_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add6~156_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~94_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~94_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[15]~330_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[15]~330_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[18]~334_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[18]~334_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[17]~329_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[17]~329_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[16]~332_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[16]~332_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~157_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~157_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3180_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3180_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3181_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3181_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3184_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3184_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3182_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3182_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3183_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3183_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[17]~328_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[17]~328_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3173_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3173_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3174_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3174_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \led~762_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \led~762_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3188_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3188_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3196_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3196_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector12~18_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector12~18_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector12~19_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector12~19_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~86_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~86_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_left~822_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_left~822_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~94_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~94_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_left~823_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_left~823_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_left[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_left[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector32~3_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector32~3_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector25~18_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector25~18_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector25~19_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector25~19_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \led_seg[1]~reg0_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \led_seg[1]~reg0_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector11~18_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector11~18_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector11~19_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector11~19_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~66_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~66_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[18]~162_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[18]~162_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[17]~164_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[17]~164_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[16]~166_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[16]~166_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_right~823_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_right~823_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[18]~212_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[18]~212_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[17]~214_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[17]~214_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[16]~216_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[16]~216_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_right~824_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_right~824_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_right[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_right[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector18~15_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector18~15_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[18]~282_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[18]~282_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[17]~284_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[17]~284_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[16]~286_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[16]~286_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_left~824_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_left~824_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[18]~298_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[18]~298_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[17]~300_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[17]~300_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[16]~302_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[16]~302_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
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