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📄 huang.vho

📁 东西和南北方向各有一组红、黄、绿灯用于指挥交通
💻 VHO
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SIGNAL \Div0|auto_generated|divider|divider|StageOut[17]~283_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[17]~283_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[17]~299_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[17]~299_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[16]~165_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[16]~165_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[16]~215_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[16]~215_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[16]~285_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[16]~285_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[16]~301_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[16]~301_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right[3]~4143_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right[3]~4143_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \clk~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \f1~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \f1~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \seconds[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \seconds[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \seconds[5]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \seconds[5]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal2~76_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal2~76_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \seconds[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \seconds[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \seconds[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \seconds[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \seconds[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \seconds[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \seconds[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \seconds[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \LessThan6~65_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \LessThan6~65_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \LessThan6~66_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \LessThan6~66_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~84_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~84_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[17]~249_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[17]~249_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[17]~250_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[17]~250_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[18]~255_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[18]~255_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[16]~253_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[16]~253_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~141_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~141_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3170_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3170_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \LessThan2~74_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \LessThan2~74_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \LessThan2~75_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \LessThan2~75_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~86_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~86_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[17]~324_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[17]~324_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[16]~322_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[16]~322_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add6~157_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add6~157_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal2~75_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal2~75_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \always4~0_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \always4~0_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~49_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~49_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~65_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~65_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~57_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~57_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~61_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~61_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[17]~191_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[17]~191_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[17]~192_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[17]~192_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~100_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~100_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~108_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~108_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~112_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~112_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[17]~188_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[17]~188_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~53_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~53_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[18]~189_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[18]~189_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[18]~190_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|StageOut[18]~190_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~116_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~116_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~96_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~96_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4141_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4141_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \LessThan2~73_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \LessThan2~73_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[18]~326_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[18]~326_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~161_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_4|add_sub_cella[4]~161_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[17]~323_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[17]~323_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4140_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4140_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4147_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4147_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4125_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4125_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \always4~379_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \always4~379_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \always4~380_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \always4~380_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \always4~381_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \always4~381_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \led~767_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \led~767_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3171_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3171_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~98_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[1]~98_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4126_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4126_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \LessThan0~82_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \LessThan0~82_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4127_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4127_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[15]~320_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[15]~320_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4128_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4128_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4129_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4129_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3172_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3172_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~104_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod1|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~104_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4130_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_right~4130_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_right~4131_I_modesel\ : std_logic_vector(6 DOWNTO 0);
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