⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 huang.vho

📁 东西和南北方向各有一组红、黄、绿灯用于指挥交通
💻 VHO
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
SIGNAL \couta[6]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[6]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[5]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[5]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal1~214_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal1~214_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[9]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[9]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[12]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[12]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[11]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[11]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[10]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[10]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal1~217_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal1~217_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[20]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[20]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[22]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[22]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[21]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[21]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[19]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[19]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[18]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[18]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[17]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[17]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[16]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[16]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[18]~325_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[18]~325_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[18]~254_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[18]~254_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[18]~333_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[18]~333_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[16]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[16]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[15]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[15]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[14]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[14]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[13]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[13]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[19]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[19]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[18]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[18]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[17]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[17]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[8]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[8]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[7]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[7]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[6]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[6]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[5]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[5]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[9]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[9]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[12]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[12]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[11]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[11]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[10]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[10]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[18]~161_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[18]~161_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[18]~211_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[18]~211_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[18]~281_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|StageOut[18]~281_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[18]~297_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|StageOut[18]~297_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|unreg_res_node[23]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|unreg_res_node[23]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[10]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[10]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[9]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[9]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[11]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[11]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[8]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[8]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal0~242_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal0~242_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[15]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[15]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[12]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[12]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[14]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[14]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[13]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[13]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal0~246_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal0~246_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal0~244_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal0~244_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[6]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[6]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[5]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[5]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[7]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[7]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal0~247_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal0~247_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|unreg_res_node[20]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|unreg_res_node[20]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[15]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[15]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[10]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[10]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[9]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[9]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[11]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[11]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[8]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[8]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[12]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[12]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[14]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[14]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[13]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[13]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[6]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[6]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[5]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[5]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[7]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[7]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[17]~163_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|StageOut[17]~163_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[17]~213_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|StageOut[17]~213_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -