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📁 东西和南北方向各有一组红、黄、绿灯用于指挥交通
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defparam \Add1|adder|result_node|cs_buffer[2]~I .lut_mask = "3CC0";
defparam \Add1|adder|result_node|cs_buffer[2]~I .operation_mode = "arithmetic";
defparam \Add1|adder|result_node|cs_buffer[2]~I .output_mode = "comb_only";
defparam \Add1|adder|result_node|cs_buffer[2]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC4_A3
flex10ke_lcell \Add1|adder|result_node|cs_buffer[1]~I (
// Equation(s):
// \Add1|adder|result_node|cs_buffer [1] = couta[1] $ \Add1|adder|result_node|cout [0]
// \Add1|adder|result_node|cout [1] = CARRY(couta[1] & \Add1|adder|result_node|cout [0])

	.dataa(vcc),
	.datab(couta[1]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add1|adder|result_node|cout [0]),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add1|adder|result_node|cs_buffer [1]),
	.regout(),
	.cout(\Add1|adder|result_node|cout [1]),
	.cascout());
// synopsys translate_off
defparam \Add1|adder|result_node|cs_buffer[1]~I .cin_used = "true";
defparam \Add1|adder|result_node|cs_buffer[1]~I .clock_enable_mode = "false";
defparam \Add1|adder|result_node|cs_buffer[1]~I .lut_mask = "3CC0";
defparam \Add1|adder|result_node|cs_buffer[1]~I .operation_mode = "arithmetic";
defparam \Add1|adder|result_node|cs_buffer[1]~I .output_mode = "comb_only";
defparam \Add1|adder|result_node|cs_buffer[1]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_A3
flex10ke_lcell \Add1|adder|result_node|cs_buffer[4]~I (
// Equation(s):
// \Add1|adder|result_node|cs_buffer [4] = couta[4] $ \Add1|adder|result_node|cout [3]
// \Add1|adder|result_node|cout [4] = CARRY(couta[4] & \Add1|adder|result_node|cout [3])

	.dataa(vcc),
	.datab(couta[4]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add1|adder|result_node|cout [3]),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add1|adder|result_node|cs_buffer [4]),
	.regout(),
	.cout(\Add1|adder|result_node|cout [4]),
	.cascout());
// synopsys translate_off
defparam \Add1|adder|result_node|cs_buffer[4]~I .cin_used = "true";
defparam \Add1|adder|result_node|cs_buffer[4]~I .clock_enable_mode = "false";
defparam \Add1|adder|result_node|cs_buffer[4]~I .lut_mask = "3CC0";
defparam \Add1|adder|result_node|cs_buffer[4]~I .operation_mode = "arithmetic";
defparam \Add1|adder|result_node|cs_buffer[4]~I .output_mode = "comb_only";
defparam \Add1|adder|result_node|cs_buffer[4]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC6_A3
flex10ke_lcell \Add1|adder|result_node|cs_buffer[3]~I (
// Equation(s):
// \Add1|adder|result_node|cs_buffer [3] = couta[3] $ \Add1|adder|result_node|cout [2]
// \Add1|adder|result_node|cout [3] = CARRY(couta[3] & \Add1|adder|result_node|cout [2])

	.dataa(vcc),
	.datab(couta[3]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add1|adder|result_node|cout [2]),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add1|adder|result_node|cs_buffer [3]),
	.regout(),
	.cout(\Add1|adder|result_node|cout [3]),
	.cascout());
// synopsys translate_off
defparam \Add1|adder|result_node|cs_buffer[3]~I .cin_used = "true";
defparam \Add1|adder|result_node|cs_buffer[3]~I .clock_enable_mode = "false";
defparam \Add1|adder|result_node|cs_buffer[3]~I .lut_mask = "3CC0";
defparam \Add1|adder|result_node|cs_buffer[3]~I .operation_mode = "arithmetic";
defparam \Add1|adder|result_node|cs_buffer[3]~I .output_mode = "comb_only";
defparam \Add1|adder|result_node|cs_buffer[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_F31
flex10ke_lcell \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I (
// Equation(s):
// \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella [3] = seconds[4] $ \Equal2~75  $ !\Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT 
// \Div1|auto_generated|divider|divider|add_sub_3|cout  = CARRY(\Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT  & (seconds[4] $ \Equal2~75 ))

	.dataa(seconds[4]),
	.datab(\Equal2~75 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella [3]),
	.regout(),
	.cout(\Div1|auto_generated|divider|divider|add_sub_3|cout ),
	.cascout());
// synopsys translate_off
defparam \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .cin_used = "true";
defparam \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .clock_enable_mode = "false";
defparam \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .lut_mask = "6960";
defparam \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .operation_mode = "arithmetic";
defparam \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .output_mode = "comb_only";
defparam \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC6_F21
flex10ke_lcell \shi_right~821_I (
// Equation(s):
// \shi_right~821  = \LessThan0~82  & \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~66  # !\LessThan0~82  & (shi_right[1])

	.dataa(vcc),
	.datab(\Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~66 ),
	.datac(shi_right[1]),
	.datad(\LessThan0~82 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\shi_right~821 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \shi_right~821_I .clock_enable_mode = "false";
defparam \shi_right~821_I .lut_mask = "CCF0";
defparam \shi_right~821_I .operation_mode = "normal";
defparam \shi_right~821_I .output_mode = "comb_only";
defparam \shi_right~821_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_F16
flex10ke_lcell \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I (
// Equation(s):
// \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella [3] = seconds[4] $ \LessThan6~65  $ \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT 
// \Div3|auto_generated|divider|divider|add_sub_3|cout  = CARRY(\Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT  & (seconds[4] $ !\LessThan6~65 ))

	.dataa(seconds[4]),
	.datab(\LessThan6~65 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella [3]),
	.regout(),
	.cout(\Div3|auto_generated|divider|divider|add_sub_3|cout ),
	.cascout());
// synopsys translate_off
defparam \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .cin_used = "true";
defparam \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .clock_enable_mode = "false";
defparam \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .lut_mask = "9690";
defparam \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .operation_mode = "arithmetic";
defparam \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .output_mode = "comb_only";
defparam \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_F28
flex10ke_lcell \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I (
// Equation(s):
// \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella [3] = \LessThan2~73  $ seconds[4] $ !\Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT 
// \Div0|auto_generated|divider|divider|add_sub_3|cout  = CARRY(\Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT  & (\LessThan2~73  $ !seconds[4]))

	.dataa(\LessThan2~73 ),
	.datab(seconds[4]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella [3]),
	.regout(),
	.cout(\Div0|auto_generated|divider|divider|add_sub_3|cout ),
	.cascout());
// synopsys translate_off
defparam \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .cin_used = "true";
defparam \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .clock_enable_mode = "false";
defparam \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .lut_mask = "6990";
defparam \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .operation_mode = "arithmetic";
defparam \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .output_mode = "comb_only";
defparam \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_F20
flex10ke_lcell \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I (
// Equation(s):
// \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella [3] = seconds[4] $ \always4~379  $ !\Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT 
// \Div2|auto_generated|divider|divider|add_sub_3|cout  = CARRY(\Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT  & (seconds[4] $ \always4~379 ))

	.dataa(seconds[4]),
	.datab(\always4~379 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella [3]),
	.regout(),
	.cout(\Div2|auto_generated|divider|divider|add_sub_3|cout ),
	.cascout());
// synopsys translate_off
defparam \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .cin_used = "true";
defparam \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .clock_enable_mode = "false";
defparam \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .lut_mask = "6960";
defparam \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .operation_mode = "arithmetic";
defparam \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .output_mode = "comb_only";
defparam \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC4_D32
flex10ke_lcell \cout[23]~I (
// Equation(s):
// cout[23] = DFFEA(\Add0|adder|unreg_res_node [23] & !\Equal0~235 , GLOBAL(\clk~dataout ), , , , , )

	.dataa(vcc),
	.datab(vcc),
	.datac(\Add0|adder|unreg_res_node [23]),
	.datad(\Equal0~235 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(cout[23]),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \cout[23]~I .clock_enable_mode = "false";
defparam \cout[23]~I .lut_mask = "00F0";
defparam \cout[23]~I .operation_mode = "normal";
defparam \cout[23]~I .output_mode = "reg_only";
defparam \cout[23]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC3_D32
flex10ke_lcell \cout[20]~I (
// Equation(s):
// cout[20] = DFFEA(\Add0|adder|result_node|cs_buffer [20] & !\Equal0~235 , GLOBAL(\clk~dataout ), , , , , )

	.dataa(vcc),
	.datab(vcc),
	.datac(\Add0|adder|result_node|cs_buffer [20]),
	.datad(\Equal0~235 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(cout[20]),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \cout[20]~I .clock_enable_mode = "false";
defparam \cout[20]~I .lut_mask = "00F0";
defparam \cout[20]~I .operation_mode = "normal";
defparam \cout[20]~I .output_mode = "reg_only";
defparam \cout[20]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC2_D35
flex10ke_lcell \cout[22]~I (
// Equation(s):
// cout[22] = DFFEA(\Add0|adder|result_node|cs_buffer [22], GLOBAL(\clk~dataout ), , , , , )

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\Add0|adder|result_node|cs_buffer [22]),
	.aclr(gnd),
	.aload(gnd),
	.clk(\clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(cout[22]),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \cout[22]~I .clock_enable_mode = "false";
defparam \cout[22]~I .lut_mask = "FF00";
defparam \cout[22]~I .operation_mode = "normal";
defparam \cout[22]~I .output_mode = "reg_only";
defparam \cout[22]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC1_D17
flex10ke_lcell \cout[21]~I (
// Equation(s):
// cout[21] = DFFEA(\Add0|adder|result_node|cs_buffer [21], GLOBAL(\clk~dataout ), , , , , )

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\Add0|adder|result_node|cs_buffer [21]),
	.aclr(gnd),
	.aload(gnd),
	.clk(\clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(cout[21]),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \cout[21]~I .clock_enable_mode = "false";
defparam \cout[21]~I .lut_mask = "FF00";
defparam \cout[21]~I .operation_mode = "normal";
defparam \cout[21]~I .output_mode = "reg_only";
defparam \cout[21]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC5_D32
flex10ke_lcell \Equal0~231_I (
// Equation(s):
12345

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