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	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella [3]),
	.regout(),
	.cout(\Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~COUT ),
	.cascout());
// synopsys translate_off
defparam \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .cin_used = "true";
defparam \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .clock_enable_mode = "false";
defparam \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .lut_mask = "1EE0";
defparam \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .operation_mode = "arithmetic";
defparam \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .output_mode = "comb_only";
defparam \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_F11
flex10ke_lcell \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I (
// Equation(s):
// \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella [3] = seconds[4] $ \LessThan6~65  $ \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT 
// \Mod3|auto_generated|divider|divider|add_sub_3|cout  = CARRY(\Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT  & (seconds[4] $ !\LessThan6~65 ))

	.dataa(seconds[4]),
	.datab(\LessThan6~65 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella [3]),
	.regout(),
	.cout(\Mod3|auto_generated|divider|divider|add_sub_3|cout ),
	.cascout());
// synopsys translate_off
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .cin_used = "true";
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .clock_enable_mode = "false";
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .lut_mask = "9690";
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .operation_mode = "arithmetic";
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .output_mode = "comb_only";
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_F4
flex10ke_lcell \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I (
// Equation(s):
// \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella [3] = \LessThan2~73  $ seconds[4] $ !\Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT 
// \Mod0|auto_generated|divider|divider|add_sub_3|cout  = CARRY(\Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT  & (\LessThan2~73  $ !seconds[4]))

	.dataa(\LessThan2~73 ),
	.datab(seconds[4]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella [3]),
	.regout(),
	.cout(\Mod0|auto_generated|divider|divider|add_sub_3|cout ),
	.cascout());
// synopsys translate_off
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .cin_used = "true";
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .clock_enable_mode = "false";
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .lut_mask = "6990";
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .operation_mode = "arithmetic";
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .output_mode = "comb_only";
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC5_F4
flex10ke_lcell \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I (
// Equation(s):
// \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella [1] = seconds[2] $ \LessThan2~75 
// \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~COUT  = CARRY(seconds[2] $ \LessThan2~75 )

	.dataa(seconds[2]),
	.datab(\LessThan2~75 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella [1]),
	.regout(),
	.cout(\Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~COUT ),
	.cascout());
// synopsys translate_off
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .clock_enable_mode = "false";
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .lut_mask = "6666";
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .operation_mode = "arithmetic";
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .output_mode = "comb_only";
defparam \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC1_F4
flex10ke_lcell \Mod0|auto_generated|divider|divider|StageOut[16]~321_I (
// Equation(s):
// \Mod0|auto_generated|divider|divider|StageOut[16]~321  = \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~86  & !\Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella [1]

	.dataa(vcc),
	.datab(vcc),
	.datac(\Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~86 ),
	.datad(\Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella [1]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod0|auto_generated|divider|divider|StageOut[16]~321 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \Mod0|auto_generated|divider|divider|StageOut[16]~321_I .clock_enable_mode = "false";
defparam \Mod0|auto_generated|divider|divider|StageOut[16]~321_I .lut_mask = "00F0";
defparam \Mod0|auto_generated|divider|divider|StageOut[16]~321_I .operation_mode = "normal";
defparam \Mod0|auto_generated|divider|divider|StageOut[16]~321_I .output_mode = "comb_only";
defparam \Mod0|auto_generated|divider|divider|StageOut[16]~321_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC5_F11
flex10ke_lcell \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I (
// Equation(s):
// \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella [1] = seconds[2] $ seconds[1]
// \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~COUT  = CARRY(seconds[2] $ seconds[1])

	.dataa(seconds[2]),
	.datab(seconds[1]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella [1]),
	.regout(),
	.cout(\Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~COUT ),
	.cascout());
// synopsys translate_off
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .clock_enable_mode = "false";
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .lut_mask = "6666";
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .operation_mode = "arithmetic";
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .output_mode = "comb_only";
defparam \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC4_F11
flex10ke_lcell \Mod3|auto_generated|divider|divider|StageOut[16]~252_I (
// Equation(s):
// \Mod3|auto_generated|divider|divider|StageOut[16]~252  = \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~84  & !\Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella [1]

	.dataa(vcc),
	.datab(vcc),
	.datac(\Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~84 ),
	.datad(\Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella [1]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod3|auto_generated|divider|divider|StageOut[16]~252 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \Mod3|auto_generated|divider|divider|StageOut[16]~252_I .clock_enable_mode = "false";
defparam \Mod3|auto_generated|divider|divider|StageOut[16]~252_I .lut_mask = "00F0";
defparam \Mod3|auto_generated|divider|divider|StageOut[16]~252_I .operation_mode = "normal";
defparam \Mod3|auto_generated|divider|divider|StageOut[16]~252_I .output_mode = "comb_only";
defparam \Mod3|auto_generated|divider|divider|StageOut[16]~252_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC3_F14
flex10ke_lcell \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I (
// Equation(s):
// \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella [3] = \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~COUT  $ (\Mod2|auto_generated|divider|divider|StageOut[17]~328  # \Mod2|auto_generated|divider|divider|StageOut[17]~329 )
// \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~COUT  = CARRY(\Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~COUT  & (\Mod2|auto_generated|divider|divider|StageOut[17]~328  # 
// \Mod2|auto_generated|divider|divider|StageOut[17]~329 ))

	.dataa(\Mod2|auto_generated|divider|divider|StageOut[17]~328 ),
	.datab(\Mod2|auto_generated|divider|divider|StageOut[17]~329 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[2]~COUT ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella [3]),
	.regout(),
	.cout(\Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~COUT ),
	.cascout());
// synopsys translate_off
defparam \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .cin_used = "true";
defparam \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .clock_enable_mode = "false";
defparam \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .lut_mask = "1EE0";
defparam \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .operation_mode = "arithmetic";
defparam \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .output_mode = "comb_only";
defparam \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_F12
flex10ke_lcell \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I (
// Equation(s):
// \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella [3] = seconds[4] $ \always4~379  $ !\Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT 
// \Mod2|auto_generated|divider|divider|add_sub_3|cout  = CARRY(\Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT  & (seconds[4] $ \always4~379 ))

	.dataa(seconds[4]),
	.datab(\always4~379 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[2]~COUT ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella [3]),
	.regout(),
	.cout(\Mod2|auto_generated|divider|divider|add_sub_3|cout ),
	.cascout());
// synopsys translate_off
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .cin_used = "true";
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .clock_enable_mode = "false";
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .lut_mask = "6960";
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .operation_mode = "arithmetic";
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .output_mode = "comb_only";
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC3_F5
flex10ke_lcell \ge_left~3178_I (
// Equation(s):
// \ge_left~3178  = \led~767  & (\led~762  & \ge_right~4128  # !\led~762  & (ge_left[1]))

	.dataa(\led~767 ),
	.datab(\ge_right~4128 ),
	.datac(ge_left[1]),
	.datad(\led~762 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\ge_left~3178 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \ge_left~3178_I .clock_enable_mode = "false";
defparam \ge_left~3178_I .lut_mask = "88A0";
defparam \ge_left~3178_I .operation_mode = "normal";
defparam \ge_left~3178_I .output_mode = "comb_only";
defparam \ge_left~3178_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC5_F12
flex10ke_lcell \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I (
// Equation(s):
// \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella [1] = seconds[2] $ \LessThan2~75 
// \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~COUT  = CARRY(seconds[2] $ !\LessThan2~75 )

	.dataa(seconds[2]),
	.datab(\LessThan2~75 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella [1]),
	.regout(),
	.cout(\Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~COUT ),
	.cascout());
// synopsys translate_off
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .clock_enable_mode = "false";
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .lut_mask = "6699";
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .operation_mode = "arithmetic";
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .output_mode = "comb_only";
defparam \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC4_F12
flex10ke_lcell \Mod2|auto_generated|divider|divider|StageOut[16]~331_I (
// Equation(s):
// \Mod2|auto_generated|divider|divider|StageOut[16]~331  = \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~94  & \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella [1]

	.dataa(vcc),
	.datab(vcc),
	.datac(\Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~94 ),
	.datad(\Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella [1]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mod2|auto_generated|divider|divider|StageOut[16]~331 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \Mod2|auto_generated|divider|divider|StageOut[16]~331_I .clock_enable_mode = "false";
defparam \Mod2|auto_generated|divider|divider|StageOut[16]~331_I .lut_mask = "F000";
defparam \Mod2|auto_generated|divider|divider|StageOut[16]~331_I .operation_mode = "normal";
defparam \Mod2|auto_generated|divider|divider|StageOut[16]~331_I .output_mode = "comb_only";
defparam \Mod2|auto_generated|divider|divider|StageOut[16]~331_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC5_A3
flex10ke_lcell \Add1|adder|result_node|cs_buffer[2]~I (
// Equation(s):
// \Add1|adder|result_node|cs_buffer [2] = couta[2] $ \Add1|adder|result_node|cout [1]
// \Add1|adder|result_node|cout [2] = CARRY(couta[2] & \Add1|adder|result_node|cout [1])

	.dataa(vcc),
	.datab(couta[2]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add1|adder|result_node|cout [1]),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add1|adder|result_node|cs_buffer [2]),
	.regout(),
	.cout(\Add1|adder|result_node|cout [2]),
	.cascout());
// synopsys translate_off
defparam \Add1|adder|result_node|cs_buffer[2]~I .cin_used = "true";
defparam \Add1|adder|result_node|cs_buffer[2]~I .clock_enable_mode = "false";
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