sa-1100.h

ARM的bootloader代码.rar

#define Ser0UDCD0	        	/* Ser. port 0 UDC Data reg.       */ \
                	        	/* end-point 0                     */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCD0)))
#define Ser0UDCWC	        	/* Ser. port 0 UDC Write Count     */ \
                	        	/* reg. end-point 0                */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCWC)))
#define Ser0UDCDR	        	/* Ser. port 0 UDC Data Reg.       */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCDR)))
#define Ser0UDCSR	        	/* Ser. port 0 UDC Status Reg.     */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCSR)))
#endif /* LANGUAGE == C */

#define UDCCR_UDD	0x00000001	/* UDC Disable                     */
#define UDCCR_UDA	0x00000002	/* UDC Active (read)               */
#define UDCCR_RESIM	0x00000004	/* Resume Interrupt Mask, per errata */
#define UDCCR_EIM	0x00000008	/* End-point 0 Interrupt Mask      */
                	        	/* (disable)                       */
#define UDCCR_RIM	0x00000010	/* Receive Interrupt Mask          */
                	        	/* (disable)                       */
#define UDCCR_TIM	0x00000020	/* Transmit Interrupt Mask         */
                	        	/* (disable)                       */
#define UDCCR_SRM	0x00000040	/* Suspend/Resume interrupt Mask   */
                	        	/* (disable)                       */
#define UDCCR_SUSIM	UDCCR_SRM	/* Per errata, SRM just masks suspend */
#define UDCCR_REM	0x00000080	/* REset interrupt Mask (disable)  */

#define UDCAR_ADD	Fld (7, 0)	/* function ADDress                */

#define UDCOMP_OUTMAXP	Fld (8, 0)	/* OUTput MAXimum Packet size - 1  */
                	        	/* [byte]                          */
#define UDCOMP_OutMaxPkt(Size)  	/* Output Maximum Packet size      */ \
                	        	/* [1..256 byte]                   */ \
                	(((Size) - 1) << FShft (UDCOMP_OUTMAXP))

#define UDCIMP_INMAXP	Fld (8, 0)	/* INput MAXimum Packet size - 1   */
                	        	/* [byte]                          */
#define UDCIMP_InMaxPkt(Size)   	/* Input Maximum Packet size       */ \
                	        	/* [1..256 byte]                   */ \
                	(((Size) - 1) << FShft (UDCIMP_INMAXP))

#define UDCCS0_OPR	0x00000001	/* Output Packet Ready (read)      */
#define UDCCS0_IPR	0x00000002	/* Input Packet Ready              */
#define UDCCS0_SST	0x00000004	/* Sent STall                      */
#define UDCCS0_FST	0x00000008	/* Force STall                     */
#define UDCCS0_DE	0x00000010	/* Data End                        */
#define UDCCS0_SE	0x00000020	/* Setup End (read)                */
#define UDCCS0_SO	0x00000040	/* Serviced Output packet ready    */
                	        	/* (write)                         */
#define UDCCS0_SSE	0x00000080	/* Serviced Setup End (write)      */

#define UDCCS1_RFS	0x00000001	/* Receive FIFO 12-bytes or more   */
                	        	/* Service request (read)          */
#define UDCCS1_RPC	0x00000002	/* Receive Packet Complete         */
#define UDCCS1_RPE	0x00000004	/* Receive Packet Error (read)     */
#define UDCCS1_SST	0x00000008	/* Sent STall                      */
#define UDCCS1_FST	0x00000010	/* Force STall                     */
#define UDCCS1_RNE	0x00000020	/* Receive FIFO Not Empty (read)   */

#define UDCCS2_TFS	0x00000001	/* Transmit FIFO 8-bytes or less   */
                	        	/* Service request (read)          */
#define UDCCS2_TPC	0x00000002	/* Transmit Packet Complete        */
#define UDCCS2_TPE	0x00000004	/* Transmit Packet Error (read)    */
#define UDCCS2_TUR	0x00000008	/* Transmit FIFO Under-Run         */
#define UDCCS2_SST	0x00000010	/* Sent STall                      */
#define UDCCS2_FST	0x00000020	/* Force STall                     */

#define UDCD0_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */

#define UDCWC_WC	Fld (4, 0)	/* Write Count                     */

#define UDCDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */

#define UDCSR_EIR	0x00000001	/* End-point 0 Interrupt Request   */
#define UDCSR_RIR	0x00000002	/* Receive Interrupt Request       */
#define UDCSR_TIR	0x00000004	/* Transmit Interrupt Request      */
#define UDCSR_SUSIR	0x00000008	/* SUSpend Interrupt Request       */
#define UDCSR_RESIR	0x00000010	/* RESume Interrupt Request        */
#define UDCSR_RSTIR	0x00000020	/* ReSeT Interrupt Request         */


/*
 * Universal Asynchronous Receiver/Transmitter (UART) control registers
 *
 * Registers
 *    Ser1UTCR0 	Serial port 1 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 0
 *              	(read/write).
 *    Ser1UTCR1 	Serial port 1 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 1
 *              	(read/write).
 *    Ser1UTCR2 	Serial port 1 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 2
 *              	(read/write).
 *    Ser1UTCR3 	Serial port 1 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 3
 *              	(read/write).
 *    Ser1UTDR  	Serial port 1 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Data Register
 *              	(read/write).
 *    Ser1UTSR0 	Serial port 1 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Status Register 0
 *              	(read/write).
 *    Ser1UTSR1 	Serial port 1 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Status Register 1 (read).
 *
 *    Ser2UTCR0 	Serial port 2 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 0
 *              	(read/write).
 *    Ser2UTCR1 	Serial port 2 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 1
 *              	(read/write).
 *    Ser2UTCR2 	Serial port 2 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 2
 *              	(read/write).
 *    Ser2UTCR3 	Serial port 2 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 3
 *              	(read/write).
 *    Ser2UTCR4 	Serial port 2 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 4
 *              	(read/write).
 *    Ser2UTDR  	Serial port 2 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Data Register
 *              	(read/write).
 *    Ser2UTSR0 	Serial port 2 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Status Register 0
 *              	(read/write).
 *    Ser2UTSR1 	Serial port 2 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Status Register 1 (read).
 *
 *    Ser3UTCR0 	Serial port 3 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 0
 *              	(read/write).
 *    Ser3UTCR1 	Serial port 3 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 1
 *              	(read/write).
 *    Ser3UTCR2 	Serial port 3 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 2
 *              	(read/write).
 *    Ser3UTCR3 	Serial port 3 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Control Register 3
 *              	(read/write).
 *    Ser3UTDR  	Serial port 3 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Data Register
 *              	(read/write).
 *    Ser3UTSR0 	Serial port 3 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Status Register 0
 *              	(read/write).
 *    Ser3UTSR1 	Serial port 3 Universal Asynchronous
 *              	Receiver/Transmitter (UART) Status Register 1 (read).
 *
 * Clocks
 *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
 *              	or 3.5795 MHz).
 *    fua, Tua  	Frequency, period of the UART communication.
 */

#define _UTCR0(Nb)	        	/* UART Control Reg. 0 [1..3]      */ \
                	(0x80010000 + ((Nb) - 1)*0x00020000)
#define _UTCR1(Nb)	        	/* UART Control Reg. 1 [1..3]      */ \
                	(0x80010004 + ((Nb) - 1)*0x00020000)
#define _UTCR2(Nb)	        	/* UART Control Reg. 2 [1..3]      */ \
                	(0x80010008 + ((Nb) - 1)*0x00020000)
#define _UTCR3(Nb)	        	/* UART Control Reg. 3 [1..3]      */ \
                	(0x8001000C + ((Nb) - 1)*0x00020000)
#define _UTCR4(Nb)	        	/* UART Control Reg. 4 [2]         */ \
                	(0x80010010 + ((Nb) - 1)*0x00020000)
#define _UTDR(Nb)	        	/* UART Data Reg. [1..3]           */ \
                	(0x80010014 + ((Nb) - 1)*0x00020000)
#define _UTSR0(Nb)	        	/* UART Status Reg. 0 [1..3]       */ \
                	(0x8001001C + ((Nb) - 1)*0x00020000)
#define _UTSR1(Nb)	        	/* UART Status Reg. 1 [1..3]       */ \
                	(0x80010020 + ((Nb) - 1)*0x00020000)

#define _Ser1UTCR0	_UTCR0 (1)	/* Ser. port 1 UART Control Reg. 0 */
#define _Ser1UTCR1	_UTCR1 (1)	/* Ser. port 1 UART Control Reg. 1 */
#define _Ser1UTCR2	_UTCR2 (1)	/* Ser. port 1 UART Control Reg. 2 */
#define _Ser1UTCR3	_UTCR3 (1)	/* Ser. port 1 UART Control Reg. 3 */
#define _Ser1UTDR	_UTDR (1)	/* Ser. port 1 UART Data Reg.      */
#define _Ser1UTSR0	_UTSR0 (1)	/* Ser. port 1 UART Status Reg. 0  */
#define _Ser1UTSR1	_UTSR1 (1)	/* Ser. port 1 UART Status Reg. 1  */

#define _Ser2UTCR0	_UTCR0 (2)	/* Ser. port 2 UART Control Reg. 0 */
#define _Ser2UTCR1	_UTCR1 (2)	/* Ser. port 2 UART Control Reg. 1 */
#define _Ser2UTCR2	_UTCR2 (2)	/* Ser. port 2 UART Control Reg. 2 */
#define _Ser2UTCR3	_UTCR3 (2)	/* Ser. port 2 UART Control Reg. 3 */
#define _Ser2UTCR4	_UTCR4 (2)	/* Ser. port 2 UART Control Reg. 4 */
#define _Ser2UTDR	_UTDR (2)	/* Ser. port 2 UART Data Reg.      */
#define _Ser2UTSR0	_UTSR0 (2)	/* Ser. port 2 UART Status Reg. 0  */
#define _Ser2UTSR1	_UTSR1 (2)	/* Ser. port 2 UART Status Reg. 1  */

#define _Ser3UTCR0	_UTCR0 (3)	/* Ser. port 3 UART Control Reg. 0 */
#define _Ser3UTCR1	_UTCR1 (3)	/* Ser. port 3 UART Control Reg. 1 */
#define _Ser3UTCR2	_UTCR2 (3)	/* Ser. port 3 UART Control Reg. 2 */
#define _Ser3UTCR3	_UTCR3 (3)	/* Ser. port 3 UART Control Reg. 3 */
#define _Ser3UTDR	_UTDR (3)	/* Ser. port 3 UART Data Reg.      */
#define _Ser3UTSR0	_UTSR0 (3)	/* Ser. port 3 UART Status Reg. 0  */
#define _Ser3UTSR1	_UTSR1 (3)	/* Ser. port 3 UART Status Reg. 1  */

#if LANGUAGE == C

#define Ser1UTCR0	        	/* Ser. port 1 UART Control Reg. 0 */ \
                	(*((volatile Word *) io_p2v (_Ser1UTCR0)))
#define Ser1UTCR1	        	/* Ser. port 1 UART Control Reg. 1 */ \
                	(*((volatile Word *) io_p2v (_Ser1UTCR1)))
#define Ser1UTCR2	        	/* Ser. port 1 UART Control Reg. 2 */ \
                	(*((volatile Word *) io_p2v (_Ser1UTCR2)))
#define Ser1UTCR3	        	/* Ser. port 1 UART Control Reg. 3 */ \
                	(*((volatile Word *) io_p2v (_Ser1UTCR3)))
#define Ser1UTDR	        	/* Ser. port 1 UART Data Reg.      */ \
                	(*((volatile Word *) io_p2v (_Ser1UTDR)))
#define Ser1UTSR0	        	/* Ser. port 1 UART Status Reg. 0  */ \
                	(*((volatile Word *) io_p2v (_Ser1UTSR0)))
#define Ser1UTSR1	        	/* Ser. port 1 UART Status Reg. 1  */ \
                	(*((volatile Word *) io_p2v (_Ser1UTSR1)))

#define Ser2UTCR0	        	/* Ser. port 2 UART Control Reg. 0 */ \
                	(*((volatile Word *) io_p2v (_Ser2UTCR0)))
#define Ser2UTCR1	        	/* Ser. port 2 UART Control Reg. 1 */ \
                	(*((volatile Word *) io_p2v (_Ser2UTCR1)))
#define Ser2UTCR2	        	/* Ser. port 2 UART Control Reg. 2 */ \
                	(*((volatile Word *) io_p2v (_Ser2UTCR2)))
#define Ser2UTCR3	        	/* Ser. port 2 UART Control Reg. 3 */ \
                	(*((volatile Word *) io_p2v (_Ser2UTCR3)))
#define Ser2UTCR4	        	/* Ser. port 2 UART Control Reg. 4 */ \
                	(*((volatile Word *) io_p2v (_Ser2UTCR4)))
#define Ser2UTDR	        	/* Ser. port 2 UART Data Reg.      */ \
                	(*((volatile Word *) io_p2v (_Ser2UTDR)))
#define Ser2UTSR0	        	/* Ser. port 2 UART Status Reg. 0  */ \
                	(*((volatile Word *) io_p2v (_Ser2UTSR0)))
#define Ser2UTSR1	        	/* Ser. port 2 UART Status Reg. 1  */ \
                	(*((volatile Word *) io_p2v (_Ser2UTSR1)))

#define Ser3UTCR0	        	/* Ser. port 3 UART Control Reg. 0 */ \
                	(*((volatile Word *) io_p2v (_Ser3UTCR0)))
#define Ser3UTCR1	        	/* Ser. port 3 UART Control Reg. 1 */ \
                	(*((volatile Word *) io_p2v (_Ser3UTCR1)))
#define Ser3UTCR2	        	/* Ser. port 3 UART Control Reg. 2 */ \
                	(*((volatile Word *) io_p2v (_Ser3UTCR2)))
#define Ser3UTCR3	        	/* Ser. port 3 UART Control Reg. 3 */ \
                	(*((volatile Word *) io_p2v (_Ser3UTCR3)))
#define Ser3UTDR	        	/* Ser. port 3 UART Data Reg.      */ \
                	(*((volatile Word *) io_p2v (_Ser3UTDR)))
#define Ser3UTSR0	        	/* Ser. port 3 UART Status Reg. 0  */ \
                	(*((volatile Word *) io_p2v (_Ser3UTSR0)))
#define Ser3UTSR1	        	/* Ser. port 3 UART Status Reg. 1  */ \
                	(*((volatile Word *) io_p2v (_Ser3UTSR1)))

#elif LANGUAGE == Assembly
#define Ser1UTCR0	( io_p2v (_Ser1UTCR0))
#define Ser1UTCR1	( io_p2v (_Ser1UTCR1))
#define Ser1UTCR2	( io_p2v (_Ser1UTCR2))
#define Ser1UTCR3	( io_p2v (_Ser1UTCR3))
#define Ser1UTDR	( io_p2v (_Ser1UTDR))