sa-1100.h

ARM的bootloader代码.rar

/*
 *	FILE    	SA-1100.h
 *
 *	Version 	1.2
 *	Author  	Copyright (c) Marc A. Viredaz, 1998
 *	        	DEC Western Research Laboratory, Palo Alto, CA
 *	Date    	January 1998 (April 1997)
 *	System  	StrongARM SA-1100
 *	Language	C or ARM Assembly
 *	Purpose 	Definition of constants related to the StrongARM
 *	        	SA-1100 microprocessor (Advanced RISC Machine (ARM)
 *	        	architecture version 4). This file is based on the
 *	        	StrongARM SA-1100 data sheet version 2.2.
 *
 *	        	Language-specific definitions are selected by the
 *	        	macro "LANGUAGE", which should be defined as either
 *	        	"C" (default) or "Assembly".
 */


#ifndef LANGUAGE
# ifdef __ASSEMBLY__
#  define LANGUAGE Assembly
# else
#  define LANGUAGE C
# endif
#endif

#ifndef io_p2v
#define io_p2v(PhAdd)	(PhAdd)
#endif

#include <asm/arch-sa1100/bitfield.h>

#define C       	0
#define Assembly	1


#if LANGUAGE == C
typedef unsigned short  Word16 ;
typedef unsigned int    Word32 ;
typedef Word32          Word ;
typedef Word            Quad [4] ;
typedef void            *Address ;
typedef void            (*ExcpHndlr) (void) ;
#endif /* LANGUAGE == C */


/*
 * Memory
 */

#define MemBnkSp	0x08000000	/* Memory Bank Space [byte]        */

#define StMemBnkSp	MemBnkSp	/* Static Memory Bank Space [byte] */
#define StMemBnk0Sp	StMemBnkSp	/* Static Memory Bank 0 Space      */
                	        	/* [byte]                          */
#define StMemBnk1Sp	StMemBnkSp	/* Static Memory Bank 1 Space      */
                	        	/* [byte]                          */
#define StMemBnk2Sp	StMemBnkSp	/* Static Memory Bank 2 Space      */
                	        	/* [byte]                          */
#define StMemBnk3Sp	StMemBnkSp	/* Static Memory Bank 3 Space      */
                	        	/* [byte]                          */

#define DRAMBnkSp	MemBnkSp	/* DRAM Bank Space [byte]          */
#define DRAMBnk0Sp	DRAMBnkSp	/* DRAM Bank 0 Space [byte]        */
#define DRAMBnk1Sp	DRAMBnkSp	/* DRAM Bank 1 Space [byte]        */
#define DRAMBnk2Sp	DRAMBnkSp	/* DRAM Bank 2 Space [byte]        */
#define DRAMBnk3Sp	DRAMBnkSp	/* DRAM Bank 3 Space [byte]        */

#define ZeroMemSp	MemBnkSp	/* Zero Memory bank Space [byte]   */

#define _StMemBnk(Nb)	        	/* Static Memory Bank [0..3]       */ \
                	(0x00000000 + (Nb)*StMemBnkSp)
#define _StMemBnk0	_StMemBnk (0)	/* Static Memory Bank 0            */
#define _StMemBnk1	_StMemBnk (1)	/* Static Memory Bank 1            */
#define _StMemBnk2	_StMemBnk (2)	/* Static Memory Bank 2            */
#define _StMemBnk3	_StMemBnk (3)	/* Static Memory Bank 3            */

#if LANGUAGE == C
typedef Quad    	StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
#define StMemBnk	        	/* Static Memory Bank [0..3]       */ \
                	((StMemBnkType *) io_p2v (_StMemBnk (0)))
#define StMemBnk0	(StMemBnk [0])	/* Static Memory Bank 0            */
#define StMemBnk1	(StMemBnk [1])	/* Static Memory Bank 1            */
#define StMemBnk2	(StMemBnk [2])	/* Static Memory Bank 2            */
#define StMemBnk3	(StMemBnk [3])	/* Static Memory Bank 3            */
#endif /* LANGUAGE == C */

#define _DRAMBnk(Nb)	        	/* DRAM Bank [0..3]                */ \
                	(0xC0000000 + (Nb)*DRAMBnkSp)
#define _DRAMBnk0	_DRAMBnk (0)	/* DRAM Bank 0                     */
#define _DRAMBnk1	_DRAMBnk (1)	/* DRAM Bank 1                     */
#define _DRAMBnk2	_DRAMBnk (2)	/* DRAM Bank 2                     */
#define _DRAMBnk3	_DRAMBnk (3)	/* DRAM Bank 3                     */

#if LANGUAGE == C
typedef Quad    	DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
#define DRAMBnk 	        	/* DRAM Bank [0..3]                */ \
                	((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
#define DRAMBnk0	(DRAMBnk [0])	/* DRAM Bank 0                     */
#define DRAMBnk1	(DRAMBnk [1])	/* DRAM Bank 1                     */
#define DRAMBnk2	(DRAMBnk [2])	/* DRAM Bank 2                     */
#define DRAMBnk3	(DRAMBnk [3])	/* DRAM Bank 3                     */
#endif /* LANGUAGE == C */

#define _ZeroMem	0xE0000000	/* Zero Memory bank                */

#if LANGUAGE == C
typedef Quad    	ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
#define ZeroMem 	        	/* Zero Memory bank                */ \
                	(*((ZeroMemType *) io_p2v (_ZeroMem)))
#endif /* LANGUAGE == C */


/*
 * Personal Computer Memory Card International Association (PCMCIA) sockets
 */

#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */

#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */

#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */

#define _PCMCIA(Nb)	        	/* PCMCIA [0..1]                   */ \
                	(0x20000000 + (Nb)*PCMCIASp)
#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]               */
#define _PCMCIAAttr(Nb)	        	/* PCMCIA Attribute [0..1]         */ \
                	(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
#define _PCMCIAMem(Nb)	        	/* PCMCIA Memory [0..1]            */ \
                	(_PCMCIA (Nb) + 3*PCMCIAPrtSp)

#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0                        */
#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O                    */
#define _PCMCIA0Attr	_PCMCIAAttr (0)	/* PCMCIA 0 Attribute              */
#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory                 */

#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1                        */
#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O                    */
#define _PCMCIA1Attr	_PCMCIAAttr (1)	/* PCMCIA 1 Attribute              */
#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory                 */

#if LANGUAGE == C

typedef Quad    	PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;

#define PCMCIA0 	        	/* PCMCIA 0                        */ \
                	(*((PCMCIAType *) io_p2v (_PCMCIA0)))
#define PCMCIA0IO	        	/* PCMCIA 0 I/O                    */ \
                	(*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
#define PCMCIA0Attr	        	/* PCMCIA 0 Attribute              */ \
                	(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
#define PCMCIA0Mem	        	/* PCMCIA 0 Memory                 */ \
                	(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))

#define PCMCIA1 	        	/* PCMCIA 1                        */ \
                	(*((PCMCIAType *) io_p2v (_PCMCIA1)))
#define PCMCIA1IO	        	/* PCMCIA 1 I/O                    */ \
                	(*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
#define PCMCIA1Attr	        	/* PCMCIA 1 Attribute              */ \
                	(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
#define PCMCIA1Mem	        	/* PCMCIA 1 Memory                 */ \
                	(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))

#endif /* LANGUAGE == C */


/*
 * Universal Serial Bus (USB) Device Controller (UDC) control registers
 *
 * Registers
 *    Ser0UDCCR 	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Control Register (read/write).
 *    Ser0UDCAR 	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Address Register (read/write).
 *    Ser0UDCOMP	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Output Maximum Packet size register
 *              	(read/write).
 *    Ser0UDCIMP	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Input Maximum Packet size register
 *              	(read/write).
 *    Ser0UDCCS0	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Control/Status register end-point 0
 *              	(read/write).
 *    Ser0UDCCS1	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Control/Status register end-point 1
 *              	(output, read/write).
 *    Ser0UDCCS2	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Control/Status register end-point 2
 *              	(input, read/write).
 *    Ser0UDCD0 	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Data register end-point 0
 *              	(read/write).
 *    Ser0UDCWC 	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Write Count register end-point 0
 *              	(read).
 *    Ser0UDCDR 	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Data Register (read/write).
 *    Ser0UDCSR 	Serial port 0 Universal Serial Bus (USB) Device
 *              	Controller (UDC) Status Register (read/write).
 */

#define _Ser0UDCCR	0x80000000	/* Ser. port 0 UDC Control Reg.    */
#define _Ser0UDCAR	0x80000004	/* Ser. port 0 UDC Address Reg.    */
#define _Ser0UDCOMP	0x80000008	/* Ser. port 0 UDC Output Maximum  */
                	        	/* Packet size reg.                */
#define _Ser0UDCIMP	0x8000000C	/* Ser. port 0 UDC Input Maximum   */
                	        	/* Packet size reg.                */
#define _Ser0UDCCS0	0x80000010	/* Ser. port 0 UDC Control/Status  */
                	        	/* reg. end-point 0                */
#define _Ser0UDCCS1	0x80000014	/* Ser. port 0 UDC Control/Status  */
                	        	/* reg. end-point 1 (output)       */
#define _Ser0UDCCS2	0x80000018	/* Ser. port 0 UDC Control/Status  */
                	        	/* reg. end-point 2 (input)        */
#define _Ser0UDCD0	0x8000001C	/* Ser. port 0 UDC Data reg.       */
                	        	/* end-point 0                     */
#define _Ser0UDCWC	0x80000020	/* Ser. port 0 UDC Write Count     */
                	        	/* reg. end-point 0                */
#define _Ser0UDCDR	0x80000028	/* Ser. port 0 UDC Data Reg.       */
#define _Ser0UDCSR	0x80000030	/* Ser. port 0 UDC Status Reg.     */

#if LANGUAGE == C
#define Ser0UDCCR	        	/* Ser. port 0 UDC Control Reg.    */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCCR)))
#define Ser0UDCAR	        	/* Ser. port 0 UDC Address Reg.    */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCAR)))
#define Ser0UDCOMP	        	/* Ser. port 0 UDC Output Maximum  */ \
                	        	/* Packet size reg.                */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCOMP)))
#define Ser0UDCIMP	        	/* Ser. port 0 UDC Input Maximum   */ \
                	        	/* Packet size reg.                */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCIMP)))
#define Ser0UDCCS0	        	/* Ser. port 0 UDC Control/Status  */ \
                	        	/* reg. end-point 0                */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCCS0)))
#define Ser0UDCCS1	        	/* Ser. port 0 UDC Control/Status  */ \
                	        	/* reg. end-point 1 (output)       */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCCS1)))
#define Ser0UDCCS2	        	/* Ser. port 0 UDC Control/Status  */ \
                	        	/* reg. end-point 2 (input)        */ \
                	(*((volatile Word *) io_p2v (_Ser0UDCCS2)))