s3c2410sio.h

利用IIS总线实现音频播放的功能实验代码

/* s3c2410Sio.h - USART header file */

/* Copyright 1999 ARM Limited */

/*
modification history
--------------------
01a,25jun99,jpd  written.
*/
#include "s3c2410.h"
#include "sioLib.h"

#ifndef __INCs3c2410Sioh 
#define __INCs3c2410Sioh

#ifdef __cplusplus
extern "C" {
#endif

/* Register description of UART */

#ifndef _ASMLANGUAGE


/* Register offsets from base address */

#define S2410_ULCON     0x0000 /*UART Line control*/
#define S2410_UCON      0x0004 /*UART Control*/
#define S2410_UFCON     0x0008 /*UART FIFO control*/
#define S2410_UMCON     0x000c /*UART Modem control*/
#define S2410_UTRSTAT   0x0010 /*UART Tx/Rx status*/
#define S2410_UERSTAT   0x0014 /*UART Rx error status*/
#define S2410_UFSTAT    0x0018 /*UART FIFO status*/
#define S2410_UMSTAT    0x001c /*UART Modem status*/
#define S2410_UTXH 		0x0020/*UART Transmission Hold*/
#define S2410_URXH 		0x0024/*UART Receive buffer*/
#define S2410_UBRDIV    0x0028 /*UART Baud rate divisor*/


/* bit definitions within ULCON register */

#define ULCON_IFRD	(1<<6)		/* Infra-Red Mode */

#define ULCON_PARITY_NONE	(0<<3)		/*No parity*/
#define ULCON_PARITY_ODD	(4<<3)		/*Odd parity*/
#define ULCON_PARITY_EVEN	(5<<3)		/*Even parity*/
#define ULCON_PARITY_FORCED_1	(6<<3)	/*Parity forced/checked as 1*/
#define ULCON_PARITY_FORCED_0	(7<<3)	/*Parity forced/checked as 0*/

#define ULCON_STOP_BIT_1		(0<<2)	/*One stop bit per frame*/
#define ULCON_STOP_BIT_2		(1<<2)	/*two stop bit per frame*/

#define ULCON_WORD_LGTH_5		(0<<0)	/*Word lengh 5 bit*/
#define ULCON_WORD_LGTH_6		(1<<0)	/*Word lengh 6 bit*/
#define ULCON_WORD_LGTH_7		(2<<0)	/*Word lengh 7 bit*/
#define ULCON_WORD_LGTH_8		(3<<0)	/*Word lengh 8 bit*/


/*bit definitions within UCON register*/
#define UCON_CLOCK_UEXTCLK		(1<<10)	/*Clock for UART baud rate 0:PCLK 1:UEXTCLK*/
#define UCON_TXINT_LVL			(1<<9)	/*Tx interrupt Type 0:Pulse 1:Level*/
#define UCON_RXINT_LVL			(1<<8)	/*Rx interrupt Type 0:Pulse 1:Level*/
#define UCON_RXTO_EN			(1<<7)	/*Rx Time Out Enable 0:disable 1:enable*/
#define UCON_RXERRINT_EN		(1<<6)	/*Rx Error Status interrupt Enable 0:disable 1:enable*/
#define UCON_LOOPBACK			(1<<5)	/*Loopback Mode 0:Normal operation 1:Loopback mode*/

#define UCON_TXMD_DIS			(0<<2)	/*Transmit Mode:00:disable*/
#define UCON_TXMD_INT_POLL			(1<<2)	/*01:interrupt or poll*/
#define UCON_TXMD_DMA_0_3		(2<<2)	/*10:DMA0 for UART0/DMA3 for UART2*/
#define UCON_TXMD_DMA_1		(3<<2)	/*11:DMA1 for UART1*/

#define UCON_RXMD_DIS			(0<<0)	/*Receive Mode:00:disable*/
#define UCON_RXMD_INT_POLL			(1<<0)	/*01:interrupt or poll*/
#define UCON_RXMD_DMA_0_3		(2<<0)	/*10:DMA0 for UART0/DMA3 for UART2*/
#define UCON_RXMD_DMA_1		(3<<0)	/*11:DMA1 for UART1*/

/*bit definitions within UFCON*/
#define UFCON_TxFIFO_TLVL_0	(0<<6)	/*Tx FIFO Trigger Level 00:empty*/
#define UFCON_TxFIFO_TLVL_4	(1<<6)	/*01:4_bype*/
#define UFCON_TxFIFO_TLVL_8	(2<<6)	/*10:8_bype*/
#define UFCON_TxFIFO_TLVL_12	(3<<6)	/*11:12_bype*/

#define UFCON_RxFIFO_TLVL_0	(0<<4)	/*Rx FIFO Trigger Level 00:empty*/
#define UFCON_RxFIFO_TLVL_4	(1<<4)	/*01:4_bype*/
#define UFCON_RxFIFO_TLVL_8	(2<<4)	/*10:8_bype*/
#define UFCON_RxFIFO_TLVL_12	(3<<4)	/*11:12_bype*/

#define UFCON_TxFIFO_RST		(1<<2)	/*Tx FIFO Reset 0:Normal 1:reset*/
#define UFCON_RxFIFO_RST		(1<<1)	/*Rx FIFO Reset 0:Normal 1:reset*/
#define UFCON_FIFO_EN			(1<<0)	/*FIFO Enable 0:Disable 1:Enable*/

/*bit definitions within UMCON*/
#define UMCON_AFC_EN			(1<<4)	/*Auto Flow Control 0:disable 1:enable*/
#define UMCON_REQSEND_1		(1<<0)	/*request to send 0:'H' level(inactivate nRTS) 1:'L'level (Activate nRTS)*/

/*bit definitions within UTRSTAT*/
#define UTRSTAT_TX_EMPTY		(1<<2)	/*Transmitter empty*/
#define UTRSTAT_TXBUFFER_EMPTY	(1<<1)	/*Transmit buffer empty*/
#define UTRSTAT_RXBUFFER_DATA_RDY	(1<<0)	/*Receive buffer data ready*/

/*bit definitions within UERSTAT*/
#define UERSTAT_FMR_ERR		(1<<2)	/*Frame Error*/
#define UERSTAT_OVERRUN_ERR	(1<<0)	/*Overrun Error*/

/*bit definitions within UFSTAT*/
#define UFSTAT_TXFIFO_FULL		(1<<9)	/*TxFIFO Full*/
#define UFSTAT_RXFIFO_FULL		(1<<8)	/*RxFIFO Full*/

/*bit difinitions within UMSTAT*/
#define UMSTAT_CTS_CHG			(1<<4)	/*Delta CTS 0:has no changed 1:has changed*/
#define UMSTAT_CTS			(1<<0)	/*nCTS status 0:activated(low) 1:not activated(high)*/

/* device and channel structures */


typedef struct
    {
    /* must be first */

    SIO_CHAN        sio;          /* standard SIO_CHAN element */

    STATUS	(*getTxChar) ();  /* installed Tx callback routine */
    STATUS	(*putRcvChar) (); /* installed Rx callback routine */
    void *	getTxArg;	/* argument to Tx callback routine */
    void *	putRcvArg;	/* argument to Rx callback routine */

    UINT32 *	regs;		/* UART registers */
    int		level;		/* Interrupt level for this device */

    UINT32	channelMode;	/* such as INT, POLL modes */
    int		baudRate;	/* the current baud rate */
    UINT32	xtal;		/* UART clock frequency */     

} S2410_SIO_CHAN;

#ifndef S2410_UART_REG_READ
#define S2410_UART_REG_READ(pChan, reg, result) \
	((result) = (*(volatile UINT32 *)((UINT32)(pChan)->regs + (reg))))
#endif

#ifndef S2410_UART_REG_WRITE
#define S2410_UART_REG_WRITE(pChan, reg, data) \
	((*(volatile UINT32 *)((UINT32)(pChan)->regs + (reg))) = (data))
#endif


/* function declarations */

extern void S2410SioInt (void );
extern void S2410SioDevInit (S2410_SIO_CHAN *pChan);

#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif
 
#endif /* __INCs2410Sioh */