📄 s3c2410.h
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/* PENDING BIT*/
#define BIT_EINT0 (0x1)
#define BIT_EINT1 (0x1<<1)
#define BIT_EINT2 (0x1<<2)
#define BIT_EINT3 (0x1<<3)
#define BIT_EINT4_7 (0x1<<4)
#define BIT_EINT8_23 (0x1<<5)
#define BIT_NOTUSED6 (0x1<<6)
#define BIT_BAT_FLT (0x1<<7)
#define BIT_TICK (0x1<<8)
#define BIT_WDT (0x1<<9)
#define BIT_TIMER0 (0x1<<10)
#define BIT_TIMER1 (0x1<<11)
#define BIT_TIMER2 (0x1<<12)
#define BIT_TIMER3 (0x1<<13)
#define BIT_TIMER4 (0x1<<14)
#define BIT_UART2 (0x1<<15)
#define BIT_LCD (0x1<<16)
#define BIT_DMA0 (0x1<<17)
#define BIT_DMA1 (0x1<<18)
#define BIT_DMA2 (0x1<<19)
#define BIT_DMA3 (0x1<<20)
#define BIT_SDI (0x1<<21)
#define BIT_SPI0 (0x1<<22)
#define BIT_UART1 (0x1<<23)
#define BIT_NOTUSED24 (0x1<<24)
#define BIT_USBD (0x1<<25)
#define BIT_USBH (0x1<<26)
#define BIT_IIC (0x1<<27)
#define BIT_UART0 (0x1<<28)
#define BIT_SPI1 (0x1<<29)
#define BIT_RTC (0x1<<30)
#define BIT_ADC (0x1<<31)
#define BIT_ALLMSK (0xffffffff)
#define BIT_SUB_ALLMSK (0x7ff)
#define BIT_SUB_ADC (0x1<<10)
#define BIT_SUB_TC (0x1<<9)
#define BIT_SUB_ERR2 (0x1<<8)
#define BIT_SUB_TXD2 (0x1<<7)
#define BIT_SUB_RXD2 (0x1<<6)
#define BIT_SUB_ERR1 (0x1<<5)
#define BIT_SUB_TXD1 (0x1<<4)
#define BIT_SUB_RXD1 (0x1<<3)
#define BIT_SUB_ERR0 (0x1<<2)
#define BIT_SUB_TXD0 (0x1<<1)
#define BIT_SUB_RXD0 (0x1<<0)
/*Interrupt vector for s3c2410b*/
#define INT_LVL_EINT0 ((unsigned int) 0)
#define INT_LVL_EINT1 ((unsigned int) 1)
#define INT_LVL_EINT2 ((unsigned int) 2)
#define INT_LVL_EINT3 ((unsigned int) 3)
#define INT_LVL_EINT4_7 ((unsigned int) 4)
#define INT_LVL_EINT8_23 ((unsigned int) 5)
#define INT_LVL_NOTUSED6 ((unsigned int) 6)
#define INT_LVL_BATT_FLT ((unsigned int) 7)
#define INT_LVL_TICK ((unsigned int) 8)
#define INT_LVL_WDT ((unsigned int) 9)
#define INT_LVL_TIMER0 ((unsigned int) 10)
#define INT_LVL_TIMER1 ((unsigned int) 11)
#define INT_LVL_TIMER2 ((unsigned int) 12)
#define INT_LVL_TIMER3 ((unsigned int) 13)
#define INT_LVL_TIMER4 ((unsigned int) 14)
#define INT_LVL_UART2 ((unsigned int) 15)
#define INT_LVL_LCD ((unsigned int) 16)
#define INT_LVL_DMA0 ((unsigned int) 17)
#define INT_LVL_DMA1 ((unsigned int) 18)
#define INT_LVL_DMA2 ((unsigned int) 19)
#define INT_LVL_DMA3 ((unsigned int) 20)
#define INT_LVL_SDI ((unsigned int) 21)
#define INT_LVL_SPI0 ((unsigned int) 22)
#define INT_LVL_UART1 ((unsigned int) 23)
#define INT_LVL_NOTUSED24 ((unsigned int) 24)
#define INT_LVL_USBD ((unsigned int) 25)
#define INT_LVL_USBH ((unsigned int) 26)
#define INT_LVL_IIC ((unsigned int) 27)
#define INT_LVL_UART0 ((unsigned int) 28)
#define INT_LVL_SPI1 ((unsigned int) 29)
#define INT_LVL_RTC ((unsigned int) 30)
#define INT_LVL_ADC ((unsigned int) 31)
#define S2410_INT_ALL_IRQ_MODE 0x0
/*CLOCK*/
/*
#ifdef FCLK_20MHZ
#define M_MDIV 0x20
#define M_PDIV 0x4
#define M_SDIV 0x2
#elif FCLK_30MHZ
#define M_MDIV 0x34
#define M_PDIV 0x4
#define M_SDIV 0x2
#elif FCLK_50MHZ
#define M_MDIV 0x5c
#define M_PDIV 0x4
#define M_SDIV 0x2
#elif FCLK_60MHZ
#define M_MDIV 0x70
#define M_PDIV 0x4
#define M_SDIV 0x2
#elif FCLK_70MHZ
#define M_MDIV 0x84
#define M_PDIV 0x4
#define M_SDIV 0x2
#elif FCLK_75MHZ
#define M_MDIV 0x8e
#define M_PDIV 0x4
#define M_SDIV 0x2
#endif
*/
/*MEMORY*/
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define B1_BWSCON DW32
#define B2_BWSCON DW16
#define B3_BWSCON DW16
#define B4_BWSCON DW16
#define B5_BWSCON DW16
#define B6_BWSCON DW32
#define B7_BWSCON DW32
/*BANK0CON*/
#define B0_Tacs 0x3 /*0clk*/
#define B0_Tcos 0x3 /*0clk*/
#define B0_Tacc 0x7 /*14clk*/
#define B0_Tcoh 0x3 /*0clk*/
#define B0_Tah 0x3 /*0clk*/
#define B0_Tacp 0x0 /**/
#define B0_PMC 0x0 /*normal*/
/*BANK1CON*/
#define B1_Tacs 0x0 /*0clk*/
#define B1_Tcos 0x0 /*0clk*/
#define B1_Tacc 0x7 /*14clk*/
#define B1_Tcoh 0x0 /*0clk*/
#define B1_Tah 0x0 /*0clk*/
#define B1_Tacp 0x0
#define B1_PMC 0x0 /*normal*/
/*BANK2CON*/
#define B2_Tacs 0x0 /*0clk*/
#define B2_Tcos 0x0 /*0clk*/
#define B2_Tacc 0x7 /*14clk*/
#define B2_Tcoh 0x0 /*0clk*/
#define B2_Tah 0x0 /*0clk*/
#define B2_Tacp 0x0
#define B2_PMC 0x0 /*normal*/
/*BANK3CON*/
#define B3_Tacs 0x0 /*0clk*/
#define B3_Tcos 0x0 /*0clk*/
#define B3_Tacc 0x7 /*14clk*/
#define B3_Tcoh 0x0 /*0clk*/
#define B3_Tah 0x0 /*0clk*/
#define B3_Tacp 0x0
#define B3_PMC 0x0 /*normal*/
/*BANK4CON*/
#define B4_Tacs 0x0 /*0clk*/
#define B4_Tcos 0x0 /*0clk*/
#define B4_Tacc 0x7 /*14clk*/
#define B4_Tcoh 0x0 /*0clk*/
#define B4_Tah 0x0 /*0clk*/
#define B4_Tacp 0x0
#define B4_PMC 0x0 /*normal*/
/*BANK5CON*/
#define B5_Tacs 0x0 /*0clk*/
#define B5_Tcos 0x0 /*0clk*/
#define B5_Tacc 0x7 /*14clk*/
#define B5_Tcoh 0x0 /*0clk*/
#define B5_Tah 0x0 /*0clk*/
#define B5_Tacp 0x0
#define B5_PMC 0x0 /*normal*/
/*BANK6CON*/
#define B6_MT 0x3/*SDRAM*/
#define B6_Trcd 0x1/*3clk*/
#define B6_SCAN 0x1/*9bit*/
/*BANK7CON*/
#define B7_MT 0x3/*SDRAM*/
#define B7_Trcd 0x1/*3clk*/
#define B7_SCAN 0x1/*9bit*/
/*REFRESH parameter*/
#define REFEN 0x1 /*Refresh enable*/
#define TREFMD 0x0 /*CBR(CAS before RAS)/Auto refresh*/
#define Trp 0x0 /*2clk*/
#define Trc 0x3 /*7clk*/
#define REFCNT 1113/*period=15.6us, HCLK=60Mhz, (2048+1-15.6*60)*/
/*ISR*/
#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xc))
#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c))
#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c))
#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
#define pISR_NOTUSED6 (*(unsigned *)(_ISR_STARTADDRESS+0x38))
#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3c))
#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c))
#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5c))
#define pISR_LCD (*(unsigned *)(_ISR_STARTADDRESS+0x60))
#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c))
#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7c))
#define pISR_NOTUSED24 (*(unsigned *)(_ISR_STARTADDRESS+0x80))
#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c))
#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0x9c))
#define ClearPending(bit) {\
rSRCPND = bit;\
rINTPND = bit;\
if(rINTPND==bit);\
}
/*Wait until rINTPND is changed for the case that the ISR is very short.*/
#ifdef __cplusplus
}
#endif
#endif /*__2410ADDR_H___*/
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