📄 prvreg.h
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#define R_CT__BANKSEL1 (S_AD9995_BANK1 | 0x007F | RT_BITFIELD)
#define R_CT__CLPOB_MASK4 (S_AD9995_BANK1 | 0x0048 | RT_BITFIELD)
#define R_CT__MISC_PREV_UPDATE (S_AD9995_BANK1 | 0x0028 | RT_BITFIELD)
#define R_CT__MISC_TST_12 (S_AD9995_BANK1 | 0x0019 | RT_BITFIELD)
#define R_CT__MISC_TST_18 (S_AD9995_BANK1 | 0x0024 | RT_BITFIELD)
#define R_CT__MISC_UPDATE (S_AD9995_BANK1 | 0x0026 | RT_BITFIELD)
#define R_CT__SGPAT_POL (S_AD9995_BANK1 | 0x004A | RT_BITFIELD)
#define R_CT__SHUT_READOUT (S_AD9995_BANK1 | 0x005A | RT_BITFIELD)
#define R_CT__SHUT_SUBCKPOL (S_AD9995_BANK1 | 0x0061 | RT_BITFIELD)
#define R_CT__TIM_CLIDIVIDE (S_AD9995_BANK1 | 0x0032 | RT_BITFIELD)
#define R_CT__TIM_H1_CTRL (S_AD9995_BANK1 | 0x0034 | RT_BITFIELD)
#define R_CT__TIM_H3_CTRL (S_AD9995_BANK1 | 0x0036 | RT_BITFIELD)
#define R_CT__TIM_HBLK_RETIME (S_AD9995_BANK1 | 0x003A | RT_BITFIELD)
#define R_CT__TIM_RG_CTRL (S_AD9995_BANK1 | 0x0038 | RT_BITFIELD)
#define R_CT__VDHD_MASTER (S_AD9995_BANK1 | 0x002C | RT_BITFIELD)
#define R_CT__VDHD_POL (S_AD9995_BANK1 | 0x002E | RT_BITFIELD)
#define R_CT__VDHD_RISE (S_AD9995_BANK1 | 0x0030 | RT_BITFIELD)
// AD9995_BANK1 registers (Direct) (index in AD9995_BANK1DReg Array)
#define R_CT_AFE_CLAMP_LEVEL (S_AD9995_BANK1 | 0x0002 | RT_DIRECT)
#define R_CT_AFE_CTL_MODE (S_AD9995_BANK1 | 0x0003 | RT_DIRECT)
#define R_CT_AFE_OPR_MODE (S_AD9995_BANK1 | 0x0000 | RT_DIRECT)
#define R_CT_AFE_VGAGAIN (S_AD9995_BANK1 | 0x0001 | RT_DIRECT)
#define R_CT_BANKSEL1 (S_AD9995_BANK1 | 0x0036 | RT_DIRECT)
#define R_CT_CLPOB_MASK01 (S_AD9995_BANK1 | 0x001C | RT_DIRECT)
#define R_CT_CLPOB_MASK23 (S_AD9995_BANK1 | 0x001D | RT_DIRECT)
#define R_CT_CLPOB_MASK4 (S_AD9995_BANK1 | 0x001E | RT_DIRECT)
#define R_CT_MISC_17 (S_AD9995_BANK1 | 0x000B | RT_DIRECT)
#define R_CT_MISC_FIELDVAL (S_AD9995_BANK1 | 0x0010 | RT_DIRECT)
#define R_CT_MISC_MODE (S_AD9995_BANK1 | 0x000F | RT_DIRECT)
#define R_CT_MISC_OSC_POWERDOWN (S_AD9995_BANK1 | 0x000A | RT_DIRECT)
#define R_CT_MISC_OUT_CONTROL (S_AD9995_BANK1 | 0x0005 | RT_DIRECT)
#define R_CT_MISC_PREV_UPDATE (S_AD9995_BANK1 | 0x000E | RT_DIRECT)
#define R_CT_MISC_SW_RST (S_AD9995_BANK1 | 0x0004 | RT_DIRECT)
#define R_CT_MISC_SYNC_POL (S_AD9995_BANK1 | 0x0007 | RT_DIRECT)
#define R_CT_MISC_SYNC_SUSP (S_AD9995_BANK1 | 0x0008 | RT_DIRECT)
#define R_CT_MISC_TGCORE_RST (S_AD9995_BANK1 | 0x0009 | RT_DIRECT)
#define R_CT_MISC_TST_12 (S_AD9995_BANK1 | 0x0006 | RT_DIRECT)
#define R_CT_MISC_TST_18 (S_AD9995_BANK1 | 0x000C | RT_DIRECT)
#define R_CT_MISC_UPDATE (S_AD9995_BANK1 | 0x000D | RT_DIRECT)
#define R_CT_SGPAT0_TOG12 (S_AD9995_BANK1 | 0x0020 | RT_DIRECT)
#define R_CT_SGPAT1_TOG12 (S_AD9995_BANK1 | 0x0021 | RT_DIRECT)
#define R_CT_SGPAT2_TOG12 (S_AD9995_BANK1 | 0x0022 | RT_DIRECT)
#define R_CT_SGPAT3_TOG12 (S_AD9995_BANK1 | 0x0023 | RT_DIRECT)
#define R_CT_SGPAT_POL (S_AD9995_BANK1 | 0x001F | RT_DIRECT)
#define R_CT_SHUT_CTRL (S_AD9995_BANK1 | 0x0024 | RT_DIRECT)
#define R_CT_SHUT_EXPOSURE (S_AD9995_BANK1 | 0x0026 | RT_DIRECT)
#define R_CT_SHUT_M_OFF_FD (S_AD9995_BANK1 | 0x002F | RT_DIRECT)
#define R_CT_SHUT_M_OFF_LNPX (S_AD9995_BANK1 | 0x0030 | RT_DIRECT)
#define R_CT_SHUT_M_ONPOS (S_AD9995_BANK1 | 0x002E | RT_DIRECT)
#define R_CT_SHUT_M_POL (S_AD9995_BANK1 | 0x002D | RT_DIRECT)
#define R_CT_SHUT_READOUT (S_AD9995_BANK1 | 0x0025 | RT_DIRECT)
#define R_CT_SHUT_STROBOFF_FD (S_AD9995_BANK1 | 0x0034 | RT_DIRECT)
#define R_CT_SHUT_STROBOFF_LNPX (S_AD9995_BANK1 | 0x0035 | RT_DIRECT)
#define R_CT_SHUT_STROBON_FD (S_AD9995_BANK1 | 0x0032 | RT_DIRECT)
#define R_CT_SHUT_STROBON_LNPX (S_AD9995_BANK1 | 0x0033 | RT_DIRECT)
#define R_CT_SHUT_STROB_POL (S_AD9995_BANK1 | 0x0031 | RT_DIRECT)
#define R_CT_SHUT_SUBCK1TOG (S_AD9995_BANK1 | 0x0029 | RT_DIRECT)
#define R_CT_SHUT_SUBCK2TOG (S_AD9995_BANK1 | 0x002A | RT_DIRECT)
#define R_CT_SHUT_SUBCKPOL (S_AD9995_BANK1 | 0x0028 | RT_DIRECT)
#define R_CT_SHUT_SUBCKSUPRESS (S_AD9995_BANK1 | 0x0027 | RT_DIRECT)
#define R_CT_SHUT_VSUB_MOD (S_AD9995_BANK1 | 0x002B | RT_DIRECT)
#define R_CT_SHUT_VSUB_ON (S_AD9995_BANK1 | 0x002C | RT_DIRECT)
#define R_CT_TIM_CLIDIVIDE (S_AD9995_BANK1 | 0x0014 | RT_DIRECT)
#define R_CT_TIM_DOUT_CTRL (S_AD9995_BANK1 | 0x001B | RT_DIRECT)
#define R_CT_TIM_DRV_CTRL (S_AD9995_BANK1 | 0x0019 | RT_DIRECT)
#define R_CT_TIM_H1_CTRL (S_AD9995_BANK1 | 0x0015 | RT_DIRECT)
#define R_CT_TIM_H3_CTRL (S_AD9995_BANK1 | 0x0016 | RT_DIRECT)
#define R_CT_TIM_HBLK_RETIME (S_AD9995_BANK1 | 0x0018 | RT_DIRECT)
#define R_CT_TIM_RG_CTRL (S_AD9995_BANK1 | 0x0017 | RT_DIRECT)
#define R_CT_TIM_SAMP_CTRL (S_AD9995_BANK1 | 0x001A | RT_DIRECT)
#define R_CT_VDHD_MASTER (S_AD9995_BANK1 | 0x0011 | RT_DIRECT)
#define R_CT_VDHD_POL (S_AD9995_BANK1 | 0x0012 | RT_DIRECT)
#define R_CT_VDHD_RISE (S_AD9995_BANK1 | 0x0013 | RT_DIRECT)
// AD9995_BANK2 registers (Bitfield) (index in AD9995_BANK2BReg Array)
#define R_CT_F0_MULTR0 (S_AD9995_BANK2 | 0x0215 | RT_BITFIELD)
#define R_CT_F0_MULTR1 (S_AD9995_BANK2 | 0x0212 | RT_BITFIELD)
#define R_CT_F0_MULTR2 (S_AD9995_BANK2 | 0x020F | RT_BITFIELD)
#define R_CT_F0_MULTR3 (S_AD9995_BANK2 | 0x020C | RT_BITFIELD)
#define R_CT_F0_MULTR4 (S_AD9995_BANK2 | 0x021F | RT_BITFIELD)
#define R_CT_F0_MULTR5 (S_AD9995_BANK2 | 0x021C | RT_BITFIELD)
#define R_CT_F0_MULTR6 (S_AD9995_BANK2 | 0x0219 | RT_BITFIELD)
#define R_CT_F0_SWEEPR0 (S_AD9995_BANK2 | 0x0216 | RT_BITFIELD)
#define R_CT_F0_SWEEPR1 (S_AD9995_BANK2 | 0x0213 | RT_BITFIELD)
#define R_CT_F0_SWEEPR2 (S_AD9995_BANK2 | 0x0210 | RT_BITFIELD)
#define R_CT_F0_SWEEPR3 (S_AD9995_BANK2 | 0x020D | RT_BITFIELD)
#define R_CT_F0_SWEEPR4 (S_AD9995_BANK2 | 0x0220 | RT_BITFIELD)
#define R_CT_F0_SWEEPR5 (S_AD9995_BANK2 | 0x021D | RT_BITFIELD)
#define R_CT_F0_SWEEPR6 (S_AD9995_BANK2 | 0x021A | RT_BITFIELD)
#define R_CT_F0_VSEQR0 (S_AD9995_BANK2 | 0x0217 | RT_BITFIELD)
#define R_CT_F0_VSEQR1 (S_AD9995_BANK2 | 0x0214 | RT_BITFIELD)
#define R_CT_F0_VSEQR2 (S_AD9995_BANK2 | 0x0211 | RT_BITFIELD)
#define R_CT_F0_VSEQR3 (S_AD9995_BANK2 | 0x020E | RT_BITFIELD)
#define R_CT_F0_VSEQR4 (S_AD9995_BANK2 | 0x0221 | RT_BITFIELD)
#define R_CT_F0_VSEQR5 (S_AD9995_BANK2 | 0x021E | RT_BITFIELD)
#define R_CT_F0_VSEQR6 (S_AD9995_BANK2 | 0x021B | RT_BITFIELD)
#define R_CT_F1_MULTR0 (S_AD9995_BANK2 | 0x0239 | RT_BITFIELD)
#define R_CT_F1_MULTR1 (S_AD9995_BANK2 | 0x0236 | RT_BITFIELD)
#define R_CT_F1_MULTR2 (S_AD9995_BANK2 | 0x0233 | RT_BITFIELD)
#define R_CT_F1_MULTR3 (S_AD9995_BANK2 | 0x0230 | RT_BITFIELD)
#define R_CT_F1_MULTR4 (S_AD9995_BANK2 | 0x0243 | RT_BITFIELD)
#define R_CT_F1_MULTR5 (S_AD9995_BANK2 | 0x0240 | RT_BITFIELD)
#define R_CT_F1_MULTR6 (S_AD9995_BANK2 | 0x023D | RT_BITFIELD)
#define R_CT_F1_SWEEPR0 (S_AD9995_BANK2 | 0x023A | RT_BITFIELD)
#define R_CT_F1_SWEEPR1 (S_AD9995_BANK2 | 0x0237 | RT_BITFIELD)
#define R_CT_F1_SWEEPR2 (S_AD9995_BANK2 | 0x0234 | RT_BITFIELD)
#define R_CT_F1_SWEEPR3 (S_AD9995_BANK2 | 0x0231 | RT_BITFIELD)
#define R_CT_F1_SWEEPR4 (S_AD9995_BANK2 | 0x0244 | RT_BITFIELD)
#define R_CT_F1_SWEEPR5 (S_AD9995_BANK2 | 0x0241 | RT_BITFIELD)
#define R_CT_F1_SWEEPR6 (S_AD9995_BANK2 | 0x023E | RT_BITFIELD)
#define R_CT_F1_VSEQR0 (S_AD9995_BANK2 | 0x023B | RT_BITFIELD)
#define R_CT_F1_VSEQR1 (S_AD9995_BANK2 | 0x0238 | RT_BITFIELD)
#define R_CT_F1_VSEQR2 (S_AD9995_BANK2 | 0x0235 | RT_BITFIELD)
#define R_CT_F1_VSEQR3 (S_AD9995_BANK2 | 0x0232 | RT_BITFIELD)
#define R_CT_F1_VSEQR4 (S_AD9995_BANK2 | 0x0245 | RT_BITFIELD)
#define R_CT_F1_VSEQR5 (S_AD9995_BANK2 | 0x0242 | RT_BITFIELD)
#define R_CT_F1_VSEQR6 (S_AD9995_BANK2 | 0x023F | RT_BITFIELD)
#define R_CT_F2_MULTR0 (S_AD9995_BANK2 | 0x025D | RT_BITFIELD)
#define R_CT_F2_MULTR1 (S_AD9995_BANK2 | 0x025A | RT_BITFIELD)
#define R_CT_F2_MULTR2 (S_AD9995_BANK2 | 0x0257 | RT_BITFIELD)
#define R_CT_F2_MULTR3 (S_AD9995_BANK2 | 0x0254 | RT_BITFIELD)
#define R_CT_F2_MULTR4 (S_AD9995_BANK2 | 0x0267 | RT_BITFIELD)
#define R_CT_F2_MULTR5 (S_AD9995_BANK2 | 0x0264 | RT_BITFIELD)
#define R_CT_F2_MULTR6 (S_AD9995_BANK2 | 0x0261 | RT_BITFIELD)
#define R_CT_F2_SWEEPR0 (S_AD9995_BANK2 | 0x025E | RT_BITFIELD)
#define R_CT_F2_SWEEPR1 (S_AD9995_BANK2 | 0x025B | RT_BITFIELD)
#define R_CT_F2_SWEEPR2 (S_AD9995_BANK2 | 0x0258 | RT_BITFIELD)
#define R_CT_F2_SWEEPR3 (S_AD9995_BANK2 | 0x0255 | RT_BITFIELD)
#define R_CT_F2_SWEEPR4 (S_AD9995_BANK2 | 0x0268 | RT_BITFIELD)
#define R_CT_F2_SWEEPR5 (S_AD9995_BANK2 | 0x0265 | RT_BITFIELD)
#define R_CT_F2_SWEEPR6 (S_AD9995_BANK2 | 0x0262 | RT_BITFIELD)
#define R_CT_F2_VSEQR0 (S_AD9995_BANK2 | 0x025F | RT_BITFIELD)
#define R_CT_F2_VSEQR1 (S_AD9995_BANK2 | 0x025C | RT_BITFIELD)
#define R_CT_F2_VSEQR2 (S_AD9995_BANK2 | 0x0259 | RT_BITFIELD)
#define R_CT_F2_VSEQR3 (S_AD9995_BANK2 | 0x0256 | RT_BITFIELD)
#define R_CT_F2_VSEQR4 (S_AD9995_BANK2 | 0x0269 | RT_BITFIELD)
#define R_CT_F2_VSEQR5 (S_AD9995_BANK2 | 0x0266 | RT_BITFIELD)
#define R_CT_F2_VSEQR6 (S_AD9995_BANK2 | 0x0263 | RT_BITFIELD)
#define R_CT_F3_MULTR0 (S_AD9995_BANK2 | 0x0281 | RT_BITFIELD)
#define R_CT_F3_MULTR1 (S_AD9995_BANK2 | 0x027E | RT_BITFIELD)
#define R_CT_F3_MULTR2 (S_AD9995_BANK2 | 0x027B | RT_BITFIELD)
#define R_CT_F3_MULTR3 (S_AD9995_BANK2 | 0x0278 | RT_BITFIELD)
#define R_CT_F3_MULTR4 (S_AD9995_BANK2 | 0x028B | RT_BITFIELD)
#define R_CT_F3_MULTR5 (S_AD9995_BANK2 | 0x0288 | RT_BITFIELD)
#define R_CT_F3_MULTR6 (S_AD9995_BANK2 | 0x0285 | RT_BITFIELD)
#define R_CT_F3_SWEEPR0 (S_AD9995_BANK2 | 0x0282 | RT_BITFIELD)
#define R_CT_F3_SWEEPR1 (S_AD9995_BANK2 | 0x027F | RT_BITFIELD)
#define R_CT_F3_SWEEPR2 (S_AD9995_BANK2 | 0x027C | RT_BITFIELD)
#define R_CT_F3_SWEEPR3 (S_AD9995_BANK2 | 0x0279 | RT_BITFIELD)
#define R_CT_F3_SWEEPR4 (S_AD9995_BANK2 | 0x028C | RT_BITFIELD)
#define R_CT_F3_SWEEPR5 (S_AD9995_BANK2 | 0x0289 | RT_BITFIELD)
#define R_CT_F3_SWEEPR6 (S_AD9995_BANK2 | 0x0286 | RT_BITFIELD)
#define R_CT_F3_VSEQR0 (S_AD9995_BANK2 | 0x0283 | RT_BITFIELD)
#define R_CT_F3_VSEQR1 (S_AD9995_BANK2 | 0x0280 | RT_BITFIELD)
#define R_CT_F3_VSEQR2 (S_AD9995_BANK2 | 0x027D | RT_BITFIELD)
#define R_CT_F3_VSEQR3 (S_AD9995_BANK2 | 0x027A | RT_BITFIELD)
#define R_CT_F3_VSEQR4 (S_AD9995_BANK2 | 0x028D | RT_BITFIELD)
#define R_CT_F3_VSEQR5 (S_AD9995_BANK2 | 0x028A | RT_BITFIELD)
#define R_CT_F3_VSEQR6 (S_AD9995_BANK2 | 0x0287 | RT_BITFIELD)
#define R_CT_F4_MULTR0 (S_AD9995_BANK2 | 0x02A5 | RT_BITFIELD)
#define R_CT_F4_MULTR1 (S_AD9995_BANK2 | 0x02A2 | RT_BITFIELD)
#define R_CT_F4_MULTR2 (S_AD9995_BANK2 | 0x029F | RT_BITFIELD)
#define R_CT_F4_MULTR3 (S_AD9995_BANK2 | 0x029C | RT_BITFIELD)
#define R_CT_F4_MULTR4 (S_AD9995_BANK2 | 0x02AF | RT_BITFIELD)
#define R_CT_F4_MULTR5 (S_AD9995_BANK2 | 0x02AC | RT_BITFIELD)
#define R_CT_F4_MULTR6 (S_AD9995_BANK2 | 0x02A9 | RT_BITFIELD)
#define R_CT_F4_SWEEPR0 (S_AD9995_BANK2 | 0x02A6 | RT_BITFIELD)
#define R_CT_F4_SWEEPR1 (S_AD9995_BANK2 | 0x02A3 | RT_BITFIELD)
#define R_CT_F4_SWEEPR2 (S_AD9995_BANK2 | 0x02A0 | RT_BITFIELD)
#define R_CT_F4_SWEEPR3 (S_AD9995_BANK2 | 0x029D | RT_BITFIELD)
#define R_CT_F4_SWEEPR4 (S_AD9995_BANK2 | 0x02B0 | RT_BITFIELD)
#define R_CT_F4_SWEEPR5 (S_AD9995_BANK2 | 0x02AD | RT_BITFIELD)
#define R_CT_F4_SWEEPR6 (S_AD9995_BANK2 | 0x02AA | RT_BITFIELD)
#define R_CT_F4_VSEQR0 (S_AD9995_BANK2 | 0x02A7 | RT_BITFIELD)
#define R_CT_F4_VSEQR1 (S_AD9995_BANK2 | 0x02A4 | RT_BITFIELD)
#define R_CT_F4_VSEQR2 (S_AD9995_BANK2 | 0x02A1 | RT_BITFIELD)
#define R_CT_F4_VSEQR3 (S_AD9995_BANK2 | 0x029E | RT_BITFIELD)
#define R_CT_F4_VSEQR4 (S_AD9995_BANK2 | 0x02B1 | RT_BITFIELD)
#define R_CT_F4_VSEQR5 (S_AD9995_BANK2 | 0x02AE | RT_BITFIELD)
#define R_CT_F4_VSEQR6 (S_AD9995_BANK2 | 0x02AB | RT_BITFIELD)
#define R_CT_F5_MULTR0 (S_AD9995_BANK2 | 0x02C9 | RT_BITFIELD)
#define R_CT_F5_MULTR1 (S_AD9995_BANK2 | 0x02C6 | RT_BITFIELD)
#define R_CT_F5_MULTR2 (S_AD9995_BANK2 | 0x02C3 | RT_BITFIELD)
#define R_CT_F5_MULTR3 (S_AD9995_BANK2 | 0x02C0 | RT_BITFIELD)
#define R_CT_F5_MULTR4 (S_AD9995_BANK2 | 0x02D3 | RT_BITFIELD)
#define R_CT_F5_MULTR5 (S_AD9995_BANK2 | 0x02D0 | RT_BITFIELD)
#define R_CT_F5_MULTR6 (S_AD9995_BANK2 | 0x02CD | RT_BITFIELD)
#define R_CT_F5_SWEEPR0 (S_AD9995_BANK2 | 0x02CA | RT_BITFIELD)
#define R_CT_F5_SWEEPR1 (S_AD9995_BANK2 | 0x02C7 | RT_BITFIELD)
#define R_CT_F5_SWEEPR2 (S_AD9995_BANK2 | 0x02C4 | RT_BITFIELD)
#define R_CT_F5_SWEEPR3 (S_AD9995_BANK2 | 0x02C1 | RT_BITFIELD)
#define R_CT_F5_SWEEPR4 (S_AD9995_BANK2 | 0x02D4 | RT_BITFIELD)
#define R_CT_F5_SWEEPR5 (S_AD9995_BANK2 | 0x02D1 | RT_BITFIELD)
#define R_CT_F5_SWEEPR6 (S_AD9995_BANK2 | 0x02CE | RT_BITFIELD)
#define R_CT_F5_VSEQR0 (S_AD9995_BANK2 | 0x02CB | RT_BITFIELD)
#define R_CT_F5_VSEQR1 (S_AD9995_BANK2 | 0x02C8 | RT_BITFIELD)
#define R_CT_F5_VSEQR2 (S_AD9995_BANK2 | 0x02C5 | RT_BITFIELD)
#define R_CT_F5_VSEQR3 (S_AD9995_BANK2 | 0x02C2 | RT_BITFIELD)
#define R_CT_F5_VSEQR4 (S_AD9995_BANK2 | 0x02D5 | RT_BITFIELD)
#define R_CT_F5_VSEQR5 (S_AD9995_BANK2 | 0x02D2 | RT_BITFIELD)
#define R_CT_F5_VSEQR6 (S_AD9995_BANK2 | 0x02CF | RT_BITFIELD)
#define R_CT_FLD0_HLASTLEN (S_AD9995_BANK2 | 0x0226 | RT_BITFIELD)
#define R_CT_FLD0_SCP1 (S_AD9995_BANK2 | 0x0223 | RT_BITFIELD)
#define R_CT_FLD0_SCP2 (S_AD9995_BANK2 | 0x0222 | RT_BITFIELD)
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