prvreg.h

相机传输图像程序源代码 拜耳模式（RAW格式文件）与RGB图像数据互相转换函数库

#define S_NX_FPGA_VINP         0x00B50000L
#define S_NX_FPGA_VOUP         0x00B40000L
#define S_NX_GPIO              0x00820000L
#define S_NX_I2C               0x00830000L
#define S_NX_LAN               0x00840000L
#define S_NX_LCD               0x00850000L
#define S_NX_MBS               0x00860000L
#define S_NX_MMIO_SYSTEM       0x008C0000L
#define S_NX_PCI_XIO           0x00870000L
#define S_NX_QVCP              0x00880000L
#define S_NX_RESET             0x00890000L
#define S_NX_SPDIF_IN          0x008A0000L
#define S_NX_SPDIF_OUT         0x008B0000L
#define S_NX_TM3260            0x008D0000L
#define S_NX_TMDEBUG           0x008E0000L
#define S_NX_VIP               0x008F0000L
#define S_NX_VIRTUAL           0x00900000L
#define S_NX_VLD               0x00910000L
#define S_OV3620               0x009D0000L
#define S_OV5610               0x009E0000L
#define S_PB0CTRL              0x002C0000L
#define S_PB0VTIM              0x00320000L
#define S_PC0CTRL              0x00330000L
#define S_PCI                  0x00030000L
#define S_PCI968               0x001A0000L
#define S_PCIBUS               0x00040000L
#define S_PCIMEM               0x00050000L
#define S_PIC452               0x00990000L
#define S_PIC452_CONF          0x009A0000L
#define S_PIIX4_GPIO           0x00440000L
#define S_PMD1CTRL             0x00340000L
#define S_PMX0CRP              0x00360000L
#define S_PMX0CTR              0x00370000L
#define S_PMX0FB               0x00380000L
#define S_PMX0PE               0x00390000L
#define S_PPD0CTRL             0x003A0000L
#define S_PV1PSM               0x00220000L
#define S_RXL_2DMAFIFO_CTRL    0x004F0000L
#define S_RXL_4DMAFIFO_CTRL    0x00500000L
#define S_RXL_FBOUT2_CTL       0x004E0000L
#define S_RXL_FBOUT3_CTL       0x004D0000L
#define S_RXL_GAINOFF_CTRL     0x00510000L
#define S_RXL_MTXCOLROT_A      0x00530000L
#define S_RXL_QUADTAP_CTRL     0x004C0000L
#define S_RXL_RGBSPLIT_CTRL    0x00520000L
#define S_RYE_FB_CTRL          0x005E0000L
#define S_RYX_BAYER55_CTRL     0x00570000L
#define S_RYX_BAYER_CTRL       0x00560000L
#define S_RYX_CLP_ID           0x00460000L
#define S_RYX_CLP_MEM          0x00490000L
#define S_RYX_CLP_SSRAM        0x00480000L
#define S_RYX_CPPROC_CTRL      0x00470000L
#define S_RYX_DF_CTRL          0x004A0000L
#define S_RYX_DMALUT           0x00690000L
#define S_RYX_DMAW_CHCTRL      0x005C0000L
#define S_RYX_DMA_CTRL         0x005A0000L
#define S_RYX_DMA_DBG          0x005B0000L
#define S_RYX_DUALTAP_CTRL     0x004B0000L
#define S_RYX_FBCH_CTRL        0x00600000L
#define S_RYX_FB_CTRL          0x005D0000L
#define S_RYX_FB_EXTCTRL       0x005F0000L
#define S_RYX_FSH_CTRL         0x00610000L
#define S_RYX_GPIO             0x00630000L
#define S_RYX_LUT_CTRL         0x00540000L
#define S_RYX_PATTERN2_CTRL    0x00580000L
#define S_RYX_PATTERN4_CTRL    0x00590000L
#define S_RYX_PHDETECT         0x006E0000L
#define S_RYX_PRGTMR_CTRL      0x006C0000L
#define S_RYX_PRGTMR_PHCTL     0x006F0000L
#define S_RYX_RGBLUT           0x006A0000L
#define S_RYX_SLUT_CTRL        0x00550000L
#define S_RYX_SRCLUT           0x00660000L
#define S_RYX_SRC_CTRL         0x00650000L
#define S_RYX_SYSCTL           0x00670000L
#define S_RYX_TIMER_CTRL       0x006B0000L
#define S_RYX_TIMER_GCTL       0x006D0000L
#define S_RYX_UART             0x00680000L
#define S_RZL_GPIO_SEL         0x00620000L
#define S_S3CFG                0x00150000L
#define S_S3ENH                0x00020000L
#define S_S3GIP                0x00210000L
#define S_S3SYS                0x00010000L
#define S_S3VGA                0x00000000L
#define S_SA0CTRL              0x00120000L
#define S_SA0STEST             0x00250000L
#define S_SA0TEST              0x00240000L
#define S_SA1BN16              0x001C0000L
#define S_SA1BN8A              0x001D0000L
#define S_SA1BN8B              0x001E0000L
#define S_SA1BN8C              0x001F0000L
#define S_SA1BN8D              0x00200000L
#define S_SA1CTRL              0x00290000L
#define S_SA1PACK              0x00280000L
#define S_SA1VTIM              0x00270000L
#define S_SAA7121              0x00780000L
#define S_SAA7146              0x002B0000L
#define S_SERPPX               0x003B0000L
#define S_T26_PLL              0x00260000L
#define S_TDA8444              0x000B0000L
#define S_TRIO                 0x002A0000L
#define S_TSTPSM               0x00230000L
#define S_TVP3025              0x000C0000L
#define S_TVP3026              0x00180000L
#define S_TW280X_CH            0x00A10000L
#define S_TW280X_SYS           0x00A00000L
#define S_TW6800_SYS           0x00760000L
#define S_TW6800_VID           0x00770000L
#define S_UNKNOWN_VGA          0x00140000L
#define S_VATTR                0x00080000L
#define S_VGA                  0x00090000L
#define S_VGA968               0x001B0000L
#define S_VGARAMDAC            0x000A0000L
#define S_VIDENG               0x00190000L
#define S_VIO                  0x000D0000L
#define S_VMEM                 0x000E0000L
#define S_VSAA_DEBI            0x00310000L
#define S_VSAA_I2C             0x00300000L
#define S_WINBONDCFG           0x00720000L
#define S_WINBOND_HWMON        0x00730000L
#define S_YPC_CLP_ACC          0x00450000L
#define S_YPC_TIMER_CTRL       0x00700000L
#define S_YPC_TIMER_GCTL       0x00710000L
#define S_YPE_GPIO             0x00640000L
#define S_YPE_SRC_CHCTRL       0x00A30000L
#define S_YPE_SRC_CTRL         0x00A20000L
#define S_Z_MHT_REGS           0x00410000L


// AD7415 registers (Bitfield) (index in AD7415BReg Array)
#define R_AD7415_FULL_PD       (S_AD7415 | 0x0002 | RT_BITFIELD)
#define R_AD7415_I2CFBYP       (S_AD7415 | 0x0003 | RT_BITFIELD)
#define R_AD7415_ONESHOT       (S_AD7415 | 0x0005 | RT_BITFIELD)
#define R_AD7415_TEMP          (S_AD7415 | 0x0001 | RT_BITFIELD)

// AD7415 registers (Direct) (index in AD7415DReg Array)
#define R_AD7415_CFG           (S_AD7415 | 0x0001 | RT_DIRECT)
#define R_AD7415_TMP           (S_AD7415 | 0x0000 | RT_DIRECT)

// AD9995_BANK1 registers (Bitfield) (index in AD9995_BANK1BReg Array)
#define R_CT_AFE_BLKLVL        (S_AD9995_BANK1 | 0x0004 | RT_BITFIELD)
#define R_CT_AFE_CLAMPLEVEL    (S_AD9995_BANK1 | 0x000C | RT_BITFIELD)
#define R_CT_AFE_CLMPEN        (S_AD9995_BANK1 | 0x0007 | RT_BITFIELD)
#define R_CT_AFE_CONTROLMODE   (S_AD9995_BANK1 | 0x000E | RT_BITFIELD)
#define R_CT_AFE_DCBYP         (S_AD9995_BANK1 | 0x0002 | RT_BITFIELD)
#define R_CT_AFE_DOUTDIS       (S_AD9995_BANK1 | 0x0011 | RT_BITFIELD)
#define R_CT_AFE_DOUTLATCH     (S_AD9995_BANK1 | 0x0010 | RT_BITFIELD)
#define R_CT_AFE_GRAYENCODE    (S_AD9995_BANK1 | 0x000F | RT_BITFIELD)
#define R_CT_AFE_PWRDOWN       (S_AD9995_BANK1 | 0x0008 | RT_BITFIELD)
#define R_CT_AFE_SLPSPEED      (S_AD9995_BANK1 | 0x0006 | RT_BITFIELD)
#define R_CT_AFE__VGAGAIN      (S_AD9995_BANK1 | 0x000A | RT_BITFIELD)
#define R_CT_CLPOB_MASK0       (S_AD9995_BANK1 | 0x0044 | RT_BITFIELD)
#define R_CT_CLPOB_MASK1       (S_AD9995_BANK1 | 0x0043 | RT_BITFIELD)
#define R_CT_CLPOB_MASK2       (S_AD9995_BANK1 | 0x0046 | RT_BITFIELD)
#define R_CT_CLPOB_MASK3       (S_AD9995_BANK1 | 0x0045 | RT_BITFIELD)
#define R_CT_MISC_FIELDV       (S_AD9995_BANK1 | 0x002A | RT_BITFIELD)
#define R_CT_MISC_OSCPD        (S_AD9995_BANK1 | 0x0021 | RT_BITFIELD)
#define R_CT_MISC_OUTCTRL      (S_AD9995_BANK1 | 0x0017 | RT_BITFIELD)
#define R_CT_MISC_RST          (S_AD9995_BANK1 | 0x0015 | RT_BITFIELD)
#define R_CT_MISC_SYNCPOL      (S_AD9995_BANK1 | 0x001B | RT_BITFIELD)
#define R_CT_MISC_SYNCSUSP     (S_AD9995_BANK1 | 0x001D | RT_BITFIELD)
#define R_CT_MISC_TGCORERST    (S_AD9995_BANK1 | 0x001F | RT_BITFIELD)
#define R_CT_MISC__MODE        (S_AD9995_BANK1 | 0x0029 | RT_BITFIELD)
#define R_CT_SGPAT0_TOG1       (S_AD9995_BANK1 | 0x004C | RT_BITFIELD)
#define R_CT_SGPAT0_TOG2       (S_AD9995_BANK1 | 0x004B | RT_BITFIELD)
#define R_CT_SGPAT1_TOG1       (S_AD9995_BANK1 | 0x004E | RT_BITFIELD)
#define R_CT_SGPAT1_TOG2       (S_AD9995_BANK1 | 0x004D | RT_BITFIELD)
#define R_CT_SGPAT2_TOG1       (S_AD9995_BANK1 | 0x0050 | RT_BITFIELD)
#define R_CT_SGPAT2_TOG2       (S_AD9995_BANK1 | 0x004F | RT_BITFIELD)
#define R_CT_SGPAT3_TOG1       (S_AD9995_BANK1 | 0x0052 | RT_BITFIELD)
#define R_CT_SGPAT3_TOG2       (S_AD9995_BANK1 | 0x0051 | RT_BITFIELD)
#define R_CT_SHUT_EXP          (S_AD9995_BANK1 | 0x0055 | RT_BITFIELD)
#define R_CT_SHUT_EXPOSE       (S_AD9995_BANK1 | 0x005C | RT_BITFIELD)
#define R_CT_SHUT_MEN          (S_AD9995_BANK1 | 0x006D | RT_BITFIELD)
#define R_CT_SHUT_MPOL         (S_AD9995_BANK1 | 0x006C | RT_BITFIELD)
#define R_CT_SHUT_MOFFFD       (S_AD9995_BANK1 | 0x0071 | RT_BITFIELD)
#define R_CT_SHUT_MOFFLIN      (S_AD9995_BANK1 | 0x0073 | RT_BITFIELD)
#define R_CT_SHUT_MOFFPIX      (S_AD9995_BANK1 | 0x0072 | RT_BITFIELD)
#define R_CT_SHUT_MONLINE      (S_AD9995_BANK1 | 0x006F | RT_BITFIELD)
#define R_CT_SHUT_MONPIX       (S_AD9995_BANK1 | 0x006E | RT_BITFIELD)
#define R_CT_SHUT_MSHUT        (S_AD9995_BANK1 | 0x0057 | RT_BITFIELD)
#define R_CT_SHUT_RDOUT        (S_AD9995_BANK1 | 0x0054 | RT_BITFIELD)
#define R_CT_SHUT_STROB        (S_AD9995_BANK1 | 0x0056 | RT_BITFIELD)
#define R_CT_SHUT_STROBOFFFD   (S_AD9995_BANK1 | 0x007B | RT_BITFIELD)
#define R_CT_SHUT_STROBOFFLIN  (S_AD9995_BANK1 | 0x007D | RT_BITFIELD)
#define R_CT_SHUT_STROBOFFPIX  (S_AD9995_BANK1 | 0x007C | RT_BITFIELD)
#define R_CT_SHUT_STROBONFD    (S_AD9995_BANK1 | 0x0077 | RT_BITFIELD)
#define R_CT_SHUT_STROBONLIN   (S_AD9995_BANK1 | 0x0079 | RT_BITFIELD)
#define R_CT_SHUT_STROBONPIX   (S_AD9995_BANK1 | 0x0078 | RT_BITFIELD)
#define R_CT_SHUT_STROBPOL     (S_AD9995_BANK1 | 0x0075 | RT_BITFIELD)
#define R_CT_SHUT_SUBCK1TOG1   (S_AD9995_BANK1 | 0x0063 | RT_BITFIELD)
#define R_CT_SHUT_SUBCK1TOG2   (S_AD9995_BANK1 | 0x0062 | RT_BITFIELD)
#define R_CT_SHUT_SUBCK2TOG1   (S_AD9995_BANK1 | 0x0065 | RT_BITFIELD)
#define R_CT_SHUT_SUBCK2TOG2   (S_AD9995_BANK1 | 0x0064 | RT_BITFIELD)
#define R_CT_SHUT_SUBCKNUM     (S_AD9995_BANK1 | 0x005E | RT_BITFIELD)
#define R_CT_SHUT_SUBCKSUPR    (S_AD9995_BANK1 | 0x005F | RT_BITFIELD)
#define R_CT_SHUT_VDHDOFF      (S_AD9995_BANK1 | 0x005D | RT_BITFIELD)
#define R_CT_SHUT_VSUB         (S_AD9995_BANK1 | 0x0058 | RT_BITFIELD)
#define R_CT_SHUT_VSUBMOD      (S_AD9995_BANK1 | 0x0067 | RT_BITFIELD)
#define R_CT_SHUT_VSUBON       (S_AD9995_BANK1 | 0x006A | RT_BITFIELD)
#define R_CT_SHUT_VSUBPOL      (S_AD9995_BANK1 | 0x0069 | RT_BITFIELD)
#define R_CT_TIM_DCK_MOD       (S_AD9995_BANK1 | 0x0041 | RT_BITFIELD)
#define R_CT_TIM_DO_DLY        (S_AD9995_BANK1 | 0x0040 | RT_BITFIELD)
#define R_CT_TIM_DO_PHASE      (S_AD9995_BANK1 | 0x0042 | RT_BITFIELD)
#define R_CT_TIM_DRVCONTROL    (S_AD9995_BANK1 | 0x003C | RT_BITFIELD)
#define R_CT_TIM_SAMPCONTROL   (S_AD9995_BANK1 | 0x003E | RT_BITFIELD)