init_sdram.c

来自「ADI BLACKFIN BF561 SDRAM读写程序」· C语言 代码 · 共 102 行

#include "cdefBF561.h"
#include "ccblkfn.h"
#include <sysreg.h>
#include <math.h>
#include "declarations.h"

#define CLKIN (30)	// clock-in frequency in MHz
#define TREF 64
#define EXP 1000
#define NRA 8192
#define SPEC_TRAS (44e-9)
#define SPEC_TRP (20e-9)
#define MHz_EXP (1e6)

void Setup_SDRAM()
{
	unsigned short SCLK_Freq, RDIV;
	unsigned short tempReg;
	
	tempReg = *pEBIU_SDSTAT;
	tempReg = tempReg & 0x0008;
	
	if(tempReg == 0x0008)
	{
		//Pass in your input clock.
		//This function will check what the core clock and system clock is based
		//on the MSEL, CSEL, and SSEL values in the PLL_CTL and PLL_DIV registers.
		SCLK_Freq = Check_Freq((unsigned short)CLKIN);
		
		//Based on the SCLK frequency derived from the previous function, this 
		//function now uses the SCLK frequency to derive the correct refresh rate.
		RDIV = Calc_Parameters(SCLK_Freq);
		
		//Finally, after the appropriate refresh rate is determined, the following
		//function initializes SDRAM using the RDIV value.
		Init_SDRAM(RDIV);	
	}
}

unsigned short Check_Freq (unsigned short Clkin_Freq)
{
	unsigned short tempReg_PLLCTL, tempReg_PLLDIV;
	unsigned short MSEL_Mult, SCLK_Mult, Divide_Frequency, SCLK, VCO_Freq;
	
	tempReg_PLLCTL = *pPLL_CTL;
	tempReg_PLLDIV = *pPLL_DIV;
	
	Divide_Frequency = tempReg_PLLCTL & 0x0001;
	if(Divide_Frequency == 1)
	{
		Clkin_Freq = Clkin_Freq/2;
	}
	
	MSEL_Mult = ((tempReg_PLLCTL & 0x7E00) >> 9);
	VCO_Freq = MSEL_Mult * Clkin_Freq;
	
	SCLK_Mult = tempReg_PLLDIV & 0x000f;
	
	SCLK = VCO_Freq/SCLK_Mult;
	
	return SCLK;
	
}

unsigned short Calc_Parameters(unsigned short SCLK_Freq)
{
	
	float clk_timing, tempReg_one; 
	int full_SCLK;
	unsigned short tras, trp, tempReg_two, RDIV;
	 
	tempReg_one = (float)(SCLK_Freq) * (float)(TREF);
	tempReg_one = tempReg_one/(float)(NRA);
	tempReg_one = ceil(tempReg_one * (float)(EXP));
	
	
	full_SCLK = (int)(SCLK_Freq)*(int)(MHz_EXP);
	clk_timing = 1/((float)(full_SCLK));
	
	tras = (unsigned short)(ceil((float)(SPEC_TRAS)/clk_timing));
	trp = (unsigned short)(ceil((float)(SPEC_TRP)/clk_timing));
	
	tempReg_two = tras + trp;
	
	RDIV = (unsigned short)(tempReg_one) - tempReg_two;

	return RDIV;	
}

void Init_SDRAM(unsigned short RDIV_Value)
{
	
	*pEBIU_SDBCTL = 0x00000015;
	ssync();
		
	*pEBIU_SDRRC = RDIV_Value;
	ssync();
	
	*pEBIU_SDGCTL = 0x0091998B;
	ssync();
}