div_3.v

占空比50 的三分频Verilog代码

module div_3(clk,clkout,rst);
input  clk,rst;
output clkout;
reg    q1,q2,q3,d;
wire clk1;

assign clk1=~clk;

always @(posedge clk or negedge rst)
  if(rst==0) q1<=1'b0;
  else if(!d)
     q1<=1'b1;
  else
     q1<=~q1;
always @(posedge clk1 or negedge rst)
if(rst==0) q2<=1'b0;
else if(!d)
     q2<=1'b1;
  else
     q2<=~q2;
always @(q1 or q2)
  d=q1&q2 ;
always @(posedge d or negedge rst)
if(rst==0) q3<=1'b0;
else q3<=~q3;

assign clkout=q3;
endmodule