phcdinc.hpp

ISP1161 USB Driver under WinCE for StrongARM processor implementation

const DWORD gcRhStatusReservedmask          = 0x7FFC7FFC;

inline PULONG HcRhStatus(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x50));   
	regBase = regBase;
	return (PULONG)0x50;
}

// Root Hub Port Status Registers Bit Masks
const DWORD gcRhPortStatusCCSmask               = 0x00000001;
const DWORD gcRhPortStatusPESmask               = 0x00000002;
const DWORD gcRhPortStatusPSSmask               = 0x00000004;
const DWORD gcRhPortStatusPOCImask              = 0x00000008;
const DWORD gcRhPortStatusPRSmask               = 0x00000010;
const DWORD gcRhPortStatusPPSmask               = 0x00000100;
const DWORD gcRhPortStatusLSDAmask              = 0x00000200;
const DWORD gcRhPortStatusCSCmask               = 0x00010000;
const DWORD gcRhPortStatusPESCmask              = 0x00020000;
const DWORD gcRhPortStatusPSSCmask              = 0x00040000;
const DWORD gcRhPortStatusOCICmask              = 0x00080000;
const DWORD gcRhPortStatusPRSCmask              = 0x00100000;
const DWORD gcRhPortStatusReservedmask          = 0xFFE0FCE0;

// considers first port to be 1.
inline PULONG HcRhPortStatus(REGISTER regBase, UINT portNum)
{       
//	return((PULONG)(regBase + 0x54 + 4 * (portNum - gcFirstRootPortNum)));   
	regBase = regBase;
	return ((PULONG)(0x54 + 4 * (portNum - gcFirstRootPortNum)));   
}



// Host Controller Communications Area

// Host Controller Communications Area info
const DWORD gcHccaByteSize                  = 256;

inline PULONG HccaInterrupt(PBYTE pHcca, UINT intrNum)
{       return((PULONG)(pHcca + 4 * intrNum));   }

inline PUSHORT HccaFrameNumber(PBYTE pHcca)
{       return((PUSHORT)(pHcca + 0x80));   }

inline PUSHORT HccaPad1(PBYTE pHcca)
{       return((PUSHORT)(pHcca + 0x82));   }

inline PULONG HccaDoneHead(PBYTE pHcca)
{       return((PULONG)(pHcca + 0x84));   }



// Descriptors

const DWORD gcEdHalted          = 0x00000001;
const DWORD gcEdToggleCarry     = 0x00000002;
const DWORD gcEdTdQueueHeadMask = 0xFFFFFFF0;

struct SEndpointDescriptor
{
    DWORD   bfFunctionAddress:7;        // bits 0-6
    DWORD   bfEndpointNumber:4;         // bits 7-10
    DWORD   bfDirection:2;              // bits 11-12
    DWORD   bfIsLowSpeed:1;             // bit 13
    DWORD   bfSkip:1;                   // bit 14
    DWORD   bfIsIsochronous:1;          // bit 15
    DWORD   bfMaxPacketSize:11;         // bits 16-26
    DWORD   bfUnused:5;                 // bits 17-31
    ULONG   paTdQueueTail;
    ULONG   paTdQueueHead;
    ULONG   paNextEd;
};

const DWORD gcPhcdPageSizeAssumption = 0x1000; //4k
const DWORD gcMaxSingleTdDataLength = 0x2000; //8K

const DWORD gcTdPidSetup        = 0x0;
const DWORD gcTdPidOut          = 0x1;
const DWORD gcTdPidIn           = 0x2;
const DWORD gcTdPidTdSetsDir    = 0x0;
const DWORD gcTdNoInterrupt     = 0x7;
const DWORD gcTdToggleUseLocal  = 0x2;
const DWORD gcTdToggleUseCarry  = 0x0;

const DWORD gcTdCCNoError                   = 0x0;
const DWORD gcTdCCCrc                       = 0x1;
const DWORD gcTdCCBitStuffing               = 0x2;
const DWORD gcTdCCDataToggleMismatch        = 0x3;
const DWORD gcTdCCStall                     = 0x4;
const DWORD gcTdCCDeviceNotResponding       = 0x5;
const DWORD gcTdCCPidCheckFailure           = 0x6;
const DWORD gcTdCCUnexpectedPid             = 0x7;
const DWORD gcTdCCDataOverrun               = 0x8;
const DWORD gcTdCCDataUnderrun              = 0x9;
const DWORD gcTdCCReserved1                 = 0xA;
const DWORD gcTdCCReserved2                 = 0xB;
const DWORD gcTdCCBufferOverrun             = 0xC;
const DWORD gcTdCCBufferUnderrun            = 0xD;
// Correct way to check for not accessed is
// if ((cc & gcTdCCNotAccessedMask) == gcTdCCNotAccessedMask)
const DWORD gcTdCCNotAccessedMask           = 0xE;

const DWORD gcITdPageMask                   = 0xFFFFF000;
const DWORD gcITdPswSizeMask                = 0x07FF;
const DWORD gcITdPswConditionCodeMask       = 0xF000;
// These are the low order bits of paBufferPage0
const DWORD gcITdAddrBitSize                = 0x00000007;
const DWORD gcITdAddrMask                   = 0x0000003F;
const DWORD gcITdEndptMask                  = 0x00000F80;

const UINT gcITdNumOffsets                  = 8;
const USHORT gcITdOffsetPageSelectBit       = 0x1000;
const USHORT gcITdOffsetMask                = 0x0FFF;
const USHORT gcITdOffsetNotAccessed         = 0xE000;

struct SGeneralTransferDescriptor
{
    DWORD   bfAddr:7;                       // bits 0-6     PHCD specific
    DWORD   bfEndptArrayNum:5;              // bits 7-11    PHCD specific
    DWORD   bfDataCounted:1;                // bits 12      PHCD specific
    DWORD   bfUnused:2;                     // bits 13-14
    DWORD   bfLastTd:1;                     // bit 15       PHCD specific
    DWORD   bfFastDataCopyRequired:1;       // bits 16      PHCD specific
    DWORD   bfIsIsoch:1;                    // bit 17       PHCD specific
    DWORD   bfShortPacketOk:1;              // bit 18
    DWORD   bfPID:2;                        // bits 19-20
    DWORD   bfDelayInterrupt:3;             // bits 21-23
    DWORD   bfDataToggle:2;                 // bits 24-25
    DWORD   bfErrorCount:2;                 // bits 26-27
    DWORD   bfConditionCode:4;              // bits 28-31
    ULONG   paCurBuffer;
    ULONG   paNextTd;
    ULONG   paBufferEnd;
};



struct SIsochTransferDescriptor
{
    DWORD   bfStartFrame:16;                // bits 0-15
    DWORD   bfFastDataCopyRequired:1;       // bits 16      PHCD specific
    DWORD   bfIsIsoch:1;                    // bit 17       PHCD specific
//  DWORD   bfUnused:3;                     // bits 18-20
	DWORD   bfCurrentFrameCount:3;			// bits 18-20
    DWORD   bfDelayInterrupt:3;             // bits 21-23
    DWORD   bfFrameCount:3;                 // bits 24-26
    DWORD   bfLastTd:1;                     // bit 27       PHCD specific
    DWORD   bfConditionCode:4;              // bits 28-31
    DWORD   paBufferPage0;                  // And with gcITdPageMask
    DWORD   paNextTd;
    DWORD   paBufferEnd;
    USHORT  offsetPsw[gcITdNumOffsets];
};


struct SPhilipsTransferDescriptor
{
    DWORD   bActualBytes:10;				// bits 0-9			PHCD specific
    DWORD   bfToggle:1;						// bits 10			PHCD specific
    DWORD   bfActive:1;                     // bits 11
	DWORD	bCompletionCode:4;				// bits 12-15
    DWORD   bMaxPacketSize:10;              // bits 16-25		PHCD specific
    DWORD   bfSpeed:1;						// bits 26			PHCD specific
    DWORD   bfLastTd:1;						// bits 27
	DWORD   bEndpointNumber:4;				// bits 28-31

    DWORD   bTotalBytes:10;					// bits 0-9,	(2nd dword)
	DWORD   bfPID:2;                        // bits 10-11,	(2nd dword) 
	DWORD   bUnused1:1;						// bits 12
	DWORD   bTokenOnce:1;					// bits 13, For Interrupt
	DWORD	bUnused2:2;						// bits 14-15,  (2nd dword)

    DWORD   bfAddr:7;						// bits 16-23,  (2nd dword)
    DWORD   bFormat:1;						// bits 24,		(2nd dword)
    DWORD   bUnused3:8;						// bits 25-31,  (2nd dword)
};



/*===============================
	ISP1161 uP register
 ===============================*/

inline PUSHORT HcRDHwConfig(REGISTER regBase)
{   
	regBase = regBase;
	return	(PUSHORT)0x20;
}
inline PUSHORT HcWRHwConfig(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xA0;
}

inline PUSHORT HcRDDMAConfig(REGISTER regBase)
{   
	regBase = regBase;
	return	(PUSHORT)0x21;
}

inline PUSHORT HcWRDMAConfig(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xA1;
}

inline PUSHORT HcRDTransCounter(REGISTER regBase)
{   
	regBase = regBase;
	return	(PUSHORT)0x22;
}

inline PUSHORT HcWRTransCounter(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xA2;
}

inline PUSHORT HcRDInterrupt(REGISTER regBase)
{   
	regBase = regBase;
	return	(PUSHORT)0x24;
}

inline PUSHORT HcWRInterrupt(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xA4;
}

inline PUSHORT HcRDInterruptEnable(REGISTER regBase)
{   
	regBase = regBase;
	return	(PUSHORT)0x25;
}

inline PUSHORT HcWRInterruptEnable(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xA5;
}

inline PUSHORT HcRDChipID(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0x27;
}

inline PUSHORT HcRDScratch(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0x28;
}
inline PUSHORT HcWRScratch(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xA8;
}

inline PUSHORT HcReset(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xA9;
}

inline PUSHORT HcRDITLBufferLength(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0x2A;
}
inline PUSHORT HcWRITLBufferLength(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xAA;
}
inline PUSHORT HcRDATLBufferLength(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0x2B;
}
inline PUSHORT HcWRATLBufferLength(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xAB;
}
inline PUSHORT HcRDBufferStatus(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0x2C;
}
inline PUSHORT HcRDBackITL0Length(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0x2D;
}
inline PUSHORT HcRDBackITL1Length(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0x2E;
}
inline PUSHORT HcRDITLBuffer(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0x40;
}
inline PUSHORT HcWRITLBuffer(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xC0;
}
inline PUSHORT HcRDATLBuffer(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0x41;
}
inline PUSHORT HcWRATLBuffer(REGISTER regBase)
{       
	regBase = regBase;
	return	(PUSHORT)0xC1;
}

#define READ_REGISTER_USHORT(reg) \
	READ_ISP1161_REGISTER_USHORT(reg)

#define WRITE_REGISTER_USHORT(reg, val) \
	WRITE_ISP1161_REGISTER_USHORT(reg, (val))


#endif //_PHCDINC_HPP_