phcdinc.hpp

ISP1161 USB Driver under WinCE for StrongARM processor implementation

/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995, 1996, 1997, 1998  Microsoft Corporation

Module Name:  
    phcdinc.hpp
    
Abstract:  
    
Notes: 
--*/
#ifndef __PHCDINC_HPP__
#define __PHCDINC_HPP__

#include <usb100.h>

const UINT gcInvalidHubNum = 0xFF;
const UINT gcUnusedPort = 0;
const UINT gcInvalidPort = 0xFF;
const UINT gcFirstRootPortNum = 1;

//Zouying
//const UINT gcMaxTransferSize                = 4 * 1024; // 4K
const UINT gcMaxTransferSize                = 896;//1023; // 1K-1, cause of PTD length is 1023

const UINT gcMaxOffsetsPerTd                = 4;
const UINT gcIsochTdErrorShift              = 12;
const UINT gcRequiredAdjustmentWait         = 6;

// Registers

// constants used to check if HC is present

const DWORD gcHcFmIntervalNominal           = 0x00002EDF;
const DWORD gcHcLSThresholdNominal          = 0x00000628;
const DWORD gcHcRevisonNominal              = 0x00000010;

// Command And Status Partition

const DWORD gcHcRevisonMask                 = 0x000000FF;

inline PULONG HcRevision(REGISTER regBase)
{       
	regBase = regBase;
	//	return((PULONG)regBase);   
	return	0;
}

//frame number mask
const DWORD gcHcFrameNumberMask             = 0x00008000;

// Control Register Bit Masks
const DWORD gcHcControlCBSRmask             = 0x00000003;
const DWORD gcHcControlCBSR1to1             = 0x00000000;
const DWORD gcHcControlCBSR2to1             = 0x00000001;
const DWORD gcHcControlCBSR3to1             = 0x00000002;
const DWORD gcHcControlCBSR4to1             = 0x00000003;

const DWORD gcHcControlPLEmask              = 0x00000004;
const DWORD gcHcControlIEmask               = 0x00000008;
const DWORD gcHcControlCLEmask              = 0x00000010;
const DWORD gcHcControlBLEmask              = 0x00000020;

const DWORD gcHcControlHCFSmask             = 0x000000C0;
const DWORD gcHcControlFSReset              = 0x00000000;
const DWORD gcHcControlFSResume             = 0x00000040;
const DWORD gcHcControlFSOperational        = 0x00000080;
const DWORD gcHcControlFSSuspend            = 0x000000C0;

const DWORD gcHcControlIRmask               = 0x00000100;
const DWORD gcHcControlRWCmask              = 0x00000200;
const DWORD gcHcControlRWEmask              = 0x00000400;
const DWORD gcHcControlReservedmask         = 0xFFFFF800;

inline PULONG HcControl(REGISTER regBase)
{       
	//return((PULONG)(regBase + 0x4));   
	regBase = regBase;
	return (PULONG)0x4;
}


// Command Register Bit Masks
const DWORD gcHcCommandStatusHCRmask        = 0x00000001;
const DWORD gcHcCommandStatusCLFmask        = 0x00000002;
const DWORD gcHcCommandStatusBLFmask        = 0x00000004;
const DWORD gcHcCommandStatusOCRmask        = 0x00000008;
const DWORD gcHcCommandStatusSOCmask        = 0x00030000;
const DWORD gcHcCommandStatusReservedmask   = 0xFFFCFFF0;

inline PULONG HcCommandStatus(REGISTER regBase)
{       
	//return((PULONG)(regBase + 0x8));   
	regBase = regBase;
	return (PULONG)0x8;   
}


// Interrupt Status Register Bit Masks
const DWORD gcHcInterruptStatusSOmask       = 0x00000001;
const DWORD gcHcInterruptStatusWDHmask      = 0x00000002;
const DWORD gcHcInterruptStatusSFmask       = 0x00000004;
const DWORD gcHcInterruptStatusRDmask       = 0x00000008;
const DWORD gcHcInterruptStatusUEmask       = 0x00000010;
const DWORD gcHcInterruptStatusFNOmask      = 0x00000020;
const DWORD gcHcInterruptStatusRHSCmask     = 0x00000040;
const DWORD gcHcInterruptStatusOCmask       = 0x40000000;
const DWORD gcHcInterruptStatusMIEmask      = 0x80000000;
const DWORD gcHcInterruptStatusReservedmask = 0x3FFFFF00;

/*
#define READ_REGISTER_ULONG(reg) \
    (*(volatile unsigned long * const)(reg))

#define WRITE_REGISTER_ULONG(reg, val) \
    (*(volatile unsigned long * const)(reg)) = (val)
*/


//	Isp-PIO Interrupt Enable Mask
const WORD gcISPSOFITLIntmask				= 0x0001;
const WORD gcISPATLIntmask					= 0x0002;
const WORD gcISPAllEOTInterrupt				= 0x0004;
const WORD gcISPOPR_RegIntmask				= 0x0010;

//	Isp-PIO Buffer Status Mask
const WORD gcISPBufferStatusISOABufferFull  = 0x0001;
const WORD gcISPBufferStatusISOBBufferFull  = 0x0002;
const WORD gcISPBufferStatusATLBufferFull   = 0x0004;
const WORD gcISPBufferStatusISOABufferDone  = 0x0008;
const WORD gcISPBufferStatusISOBBufferDone  = 0x0010;
const WORD gcISPBufferStatusATLBufferDone   = 0x0020;

//  Isp Completioncode mask
const WORD gcPTDCompletionCodemask			= 0x3;
const DWORD gcGTDDataToggleMSBmask			= 0x2;


extern "C" ULONG READ_ISP1161_REGISTER_ULONG(PULONG);
extern "C" ULONG WRITE_ISP1161_REGISTER_ULONG(PULONG, ULONG);

#define READ_REGISTER_ULONG(reg) \
    READ_ISP1161_REGISTER_ULONG(reg)

#define WRITE_REGISTER_ULONG(reg, val) \
    WRITE_ISP1161_REGISTER_ULONG(reg, (val))


inline PULONG HcInterruptStatus(REGISTER regBase)
{       
//	return((PULONG)(regBase + 0xC));   
	regBase = regBase;;
	return	(PULONG)0xC;   
}

inline PULONG HcInterruptEnable(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x10));   
	regBase = regBase;
	return	(PULONG)0x10;   
}

inline PULONG HcInterruptDisable(REGISTER regBase)
{       
	//return((PULONG)(regBase + 0x14));   
	regBase = regBase;
	return	(PULONG)0x14;   
}

// Memory Pointer Partition
inline PULONG HcHCCA(REGISTER regBase)
{       
//	return((PULONG)(regBase + 0x18));   
	regBase = regBase;
	return	(PULONG)0x18;   
}

inline PULONG HcPeriodCurrentEd(REGISTER regBase)
{   
	//return((PULONG)(regBase + 0x1C));   
	regBase = regBase;
	return (PULONG)0x1C;
}

inline PULONG HcControlHeadEd(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x20));   
	regBase = regBase;
	return (PULONG)0x20;
}

inline PULONG HcControlCurrentEd(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x24));   
	regBase = regBase;
	return (PULONG)0x24;
}

inline PULONG HcBulkHeadEd(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x28));   
	regBase = regBase;
	return (PULONG)0x28;
}

inline PULONG HcBulkCurrentEd(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x2C));   
	regBase = regBase;
	return (PULONG)0x2C;
}

inline PULONG HcDoneHead(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x30));   
	regBase = regBase;
	return (PULONG)0x30;
}


// Frame Counter Partition

// Frame Interval Register Bit Masks
const DWORD gcHcFmIntervalFImask            = 0x00003FFF;
const DWORD gcHcFmIntervalFSMPSmask         = 0x7FFF0000;
const DWORD gcHcFmIntervalFITmask           = 0x80000000;
const DWORD gcHcFmIntervalReservedmask      = 0x0000C000;
const DWORD gcHcFmIntervalMaxOverhead       = 210;


// max transfer possible is 1023 bytes.
const DWORD gcHcFmIntervalFSMPSsetting      = (1023 * 8) << 16;

inline PULONG HcFmInterval(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x34));   
	regBase = regBase;
	return (PULONG)0x34;
}


// Frame Remaining Register Bit Masks
const DWORD gcHcFmRemainingFRmask           = 0x00003FFF;
const DWORD gcHcFmRemainingFRTmask          = 0x80000000;
const DWORD gcHcFmRemainingReservedmask     = 0x3FFFC000;

inline PULONG HcFmRemaining(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x38));   
	regBase = regBase;
	return (PULONG)0x38;
}


// Frame Number Register Bit Masks
const DWORD gcHcFmNumberFNmask              = 0x0000FFFF;
const DWORD gcHcFmNumberReservedmask        = 0xFFFF0000;

inline PULONG HcFmNumber(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x3C));   
	regBase = regBase;
	return (PULONG)0x3C;
}


// Periodic Start Register Bit Masks
const DWORD gcHcPeriodicStartPSmask         = 0x00003FFF;
const DWORD gcHcPeriodicStartReservedmask   = 0xFFFFC000;

inline PULONG HcPeriodicStart(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x40));   
	regBase = regBase;
	return (PULONG)0x40;
}


// LS Threshold Register Bit Masks
const DWORD gcHcLSThresholdLSTmask          = 0x00000FFF;
const DWORD gcHcLSThresholdReservedmask     = 0xFFFFF000;

inline PULONG HcLSThreshold(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x44));   
	regBase = regBase;
	return (PULONG)0x44;
}

// Root Hub Partition

// Root Hub Descriptor A Bit Masks;
const DWORD gcRhDescriptorANDPmask          = 0x000000FF;
const DWORD gcRhDescriptorAPSMmask          = 0x00000100;
const DWORD gcRhDescriptorANPSmask          = 0x00000200;
const DWORD gcRhDescriptorADTmask           = 0x00000400;
const DWORD gcRhDescriptorAOCPMmask         = 0x00000800;
const DWORD gcRhDescriptorANOCPmask         = 0x00001000;
const DWORD gcRhDescriptorAPOTPGTmask       = 0xFF000000;
const DWORD gcRhDescriptorAReservedmask     = 0x00FFE000;

inline PULONG HcRhDescriptorA(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x48));   
	regBase = regBase;
	return (PULONG)0x48;
}


// Root Hub Descriptor B Bit Masks
const DWORD gcRhDescriptorBDRmask           = 0x0000FFFF;
const DWORD gcRhDescriptorBPPCMmask         = 0xFFFF0000;

inline PULONG HcRhDescriptorB(REGISTER regBase)
{
//	return((PULONG)(regBase + 0x4C));   
	regBase = regBase;
	return (PULONG)0x4C;
}


// Root Hub Status Register Bit Masks
const DWORD gcRhStatusLPSmask               = 0x00000001;
const DWORD gcRhStatusOCImask               = 0x00000002;
const DWORD gcRhStatusDRWEmask              = 0x00008000;
const DWORD gcRhStatusLPSCmask              = 0x00010000;
const DWORD gcRhStatusOCICmask              = 0x00020000;
const DWORD gcRhStatusCRWEmask              = 0x80000000;