phcd.hpp

ISP1161 USB Driver under WinCE for StrongARM processor implementation

	ULONG							m_HcControlBLE;

	ULONG							m_HcCommandCLF;
	ULONG							m_HcCommandBLF;


	inline VOID STRONGARM_DELAY(ULONG u_delayTimes)
	{
		for(uTesting = 0; uTesting<u_delayTimes; uTesting++);
	}

	inline USHORT READ_ISP1161_REGISTER_USHORT(PUSHORT reg) 
	{
		WRITE_PORT_USHORT((PUSHORT)(m_regBase+2), (USHORT)reg);
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif
		
		USHORT temp = READ_PORT_USHORT((PUSHORT)m_regBase);
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif
		return temp;
	}
 
	inline void WRITE_ISP1161_REGISTER_USHORT(PUSHORT reg, USHORT val) 
	{
  		
		WRITE_PORT_USHORT((PUSHORT)(m_regBase +2),(USHORT)reg);
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif

		WRITE_PORT_USHORT((PUSHORT)m_regBase, (USHORT)val);
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif
	}

	
	inline ULONG READ_ISP1161_REGISTER_ULONG(PULONG reg) 
	{

	//	USHORT tempreg = (USHORT)reg - (USHORT)p_DataPort;
	//	tempreg = tempreg /4;

		USHORT tempreg = (USHORT)reg/4;
		
		//Zouying, to access registers not existant
		if ( (tempreg >=0x6 && tempreg <=0xC) || tempreg == 0x10)
		{
			switch (tempreg)
			{
			case 0x06:
				return m_HcHCCA;
			case 0x07:
				return m_HcPeriodCurrentED;
			case 0x08:
				return m_HcControlHeadED;
			case 0x09:
				return m_HcControlCurrentED;
			case 0x0A:
				return m_HcBulkHeadED;
			case 0x0B:
				return m_HcBulkCurrentED;
			case 0x0C:
				return m_HcDoneHead;
			case 0x10:
				return m_HcPeriodicStart;
			default:
				return 0;
			}
		}
			

		WRITE_PORT_USHORT((PUSHORT)(m_regBase +2), tempreg);
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif
		USHORT temp1 = READ_PORT_USHORT((PUSHORT)m_regBase);
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif
		ULONG  temp2 = READ_PORT_USHORT((PUSHORT)m_regBase)<<16; 
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif

		temp2 |= temp1;

		//Zouying, to access HcControl bits, which is not existant
		//We need to add the values in. 

		if (tempreg == 0x01)
		{
			temp2 &= ~gcHcControlCBSRmask;
			temp2 |= m_HcControlCBSR;

			temp2 |= m_HcControlPLE;
			temp2 |= m_HcControlIE;
			temp2 |= m_HcControlCLE;
			temp2 |= m_HcControlBLE;
		}
		
		if (tempreg == 0x02)
		{
			temp2 |= m_HcCommandCLF;
			temp2 |= m_HcCommandBLF;
			
		}

		return temp2;

	}
 
	inline void WRITE_ISP1161_REGISTER_ULONG(PULONG reg, ULONG val) 
	{
  		
	//	USHORT tempreg = (USHORT)reg - (USHORT)p_DataPort;
	//	tempreg = tempreg /4;
		USHORT tempreg = (USHORT)reg/4;

		if ( (tempreg >=0x6 && tempreg <=0xC) || tempreg == 0x10)
		{
			switch (tempreg)
			{
			case 0x06:
				m_HcHCCA = val;
				break;
			case 0x07:
				m_HcPeriodCurrentED = val;
				break;
			case 0x08:
				m_HcControlHeadED = val;
				break;
			case 0x09:
				m_HcControlCurrentED = val;
				break;
			case 0x0A:
				m_HcBulkHeadED = val;
				break;
			case 0x0B:
				m_HcBulkCurrentED = val; 
				break;
			case 0x0C:
				m_HcDoneHead = val;
				break;
			case 0x10:
				m_HcPeriodicStart = val;
				break;
			default:
				return;
			}
			return;
		}

		//If writing to control register, we need to capture the last 6 bits.
		if (tempreg == 0x01)
		{
			m_HcControlCBSR = val & gcHcControlCBSRmask;
			m_HcControlPLE	= val & gcHcControlPLEmask;
			m_HcControlIE	= val & gcHcControlIEmask;
			m_HcControlCLE	= val & gcHcControlCLEmask;
			m_HcControlBLE	= val & gcHcControlBLEmask;
		}
		
		//If writing to command register, we need capture to store the CLF and BLF
		if (tempreg == 0x02)
		{
			m_HcCommandCLF = val & gcHcCommandStatusCLFmask;
			m_HcCommandBLF	= val & gcHcCommandStatusBLFmask;
			
		}

		tempreg += 0x80;

		WRITE_PORT_USHORT((PUSHORT)(m_regBase+2), tempreg);
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif
		WRITE_PORT_USHORT((PUSHORT)m_regBase, (USHORT)val);
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif
		WRITE_PORT_USHORT((PUSHORT)m_regBase, (USHORT)(val>>16));
		#ifdef PLAT_STRONGARM		
			STRONGARM_DELAY(10);
		#endif
	}

	// Helper inline functions.

	// Warning!       the following functions can all overwrite eachother
	//                because they all access the HcCommandStatus Register!!!

	inline void
	ClearControlListFilledBit(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcCommandStatus(regBase));
		dwValue &= ~gcHcCommandStatusCLFmask;
		WRITE_REGISTER_ULONG(HcCommandStatus(regBase), dwValue);
	}

	inline void
	SetControlListFilledBit(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcCommandStatus(regBase));
		dwValue |= gcHcCommandStatusCLFmask;
		WRITE_REGISTER_ULONG(HcCommandStatus(regBase), dwValue);
	}

	inline void
	ClearBulkListFilledBit(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcCommandStatus(regBase));
		dwValue &= ~gcHcCommandStatusBLFmask;
		WRITE_REGISTER_ULONG(HcCommandStatus(regBase), dwValue);
	}

	inline void
	SetBulkListFilledBit(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcCommandStatus(regBase));
		dwValue |= gcHcCommandStatusBLFmask;
		WRITE_REGISTER_ULONG(HcCommandStatus(regBase), dwValue);
	}

	// WARNING!       the following functions can all overwrite eachother
	//                because they all access the HcControl Register!!!
	inline void
	EnableAllLists(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcControl(regBase));
		dwValue |=
			gcHcControlPLEmask  |   // Periodic List
			gcHcControlIEmask   |   // Isochronous
			gcHcControlCLEmask  |   // Control List
			gcHcControlBLEmask;     // Bulk List
		WRITE_REGISTER_ULONG(HcControl(regBase), dwValue);
	}

	inline void
	DisableAllLists(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcControl(regBase));
		dwValue &= ~(gcHcControlPLEmask | gcHcControlIEmask | gcHcControlCLEmask |
			gcHcControlBLEmask);
		WRITE_REGISTER_ULONG(HcControl(regBase), dwValue);
	}


	inline void
	EnableControlList(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcControl(regBase)) | gcHcControlCLEmask;
		WRITE_REGISTER_ULONG(HcControl(regBase), dwValue);
	}

	inline void
	DisableControlList(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcControl(regBase)) & ~gcHcControlCLEmask;
		WRITE_REGISTER_ULONG(HcControl(regBase), dwValue);
	}


	inline void
	EnableBulkList(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcControl(regBase)) | gcHcControlBLEmask;
		WRITE_REGISTER_ULONG(HcControl(regBase), dwValue);
	}

	inline void
	DisableBulkList(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcControl(regBase)) & ~gcHcControlBLEmask;
		WRITE_REGISTER_ULONG(HcControl(regBase), dwValue);
	}


	inline void
	EnableIntrAndIsochLists(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcControl(regBase)) |
			gcHcControlPLEmask | gcHcControlIEmask;
		WRITE_REGISTER_ULONG(HcControl(regBase), dwValue);
	}

	inline void
	DisableIntrAndIsochLists(REGISTER regBase)
	{
		ULONG dwValue;
		dwValue = READ_REGISTER_ULONG(HcControl(regBase)) &
			~(gcHcControlPLEmask | gcHcControlIEmask);
		WRITE_REGISTER_ULONG(HcControl(regBase), dwValue);
	}

};



inline UINT
CalcHubIntrDataSize(UINT numPorts)
{
    // Calculate the number of bytes needed to hold interrupt data for
    // this number of ports.  Need 1 bit per port and bit zero is reserved.
    return(((numPorts + 1) / 8) + 1);
}

extern "C"
{

BOOL HcdGetFrameNumber(LPVOID lpvHcd, LPDWORD lpdwFrameNumber);
BOOL HcdGetFrameLength(LPVOID lpvHcd, LPUSHORT lpuFrameLength);
BOOL HcdSetFrameLength(LPVOID lpvHcd, HANDLE hEvent, USHORT uFrameLength);
BOOL HcdStopAdjustingFrame(LPVOID lpvHcd);


BOOL HcdOpenPipe(LPVOID lpvHcd, UINT iDevice,
                 LPCUSB_ENDPOINT_DESCRIPTOR lpEndpointDescriptor,
                 LPUINT lpiEndpointIndex);
BOOL HcdClosePipe(LPVOID lpvHcd, UINT iDevice, UINT iEndpointIndex);
BOOL HcdResetPipe(LPVOID lpvHcd, UINT iDevice, UINT iEndpointIndex);
BOOL HcdIsPipeHalted(LPVOID lpvHcd, UINT iDevice, UINT iEndpointIndex,
        LPBOOL lpbHalted);


BOOL HcdIssueTransfer(LPVOID lpvHcd, UINT iDevice, UINT iEndpointIndex,
                      LPTRANSFER_NOTIFY_ROUTINE lpStartAddress,
                      LPVOID lpvNotifyParameter, DWORD dwFlags,
                      LPCVOID lpvControlHeader, DWORD dwStartingFrame,
                      DWORD dwFrames, LPCDWORD aLengths, DWORD dwBufferSize,
                      LPVOID lpvBuffer, ULONG paBuffer, LPCVOID lpvCancelId,
                      LPDWORD adwIsochErrors, LPDWORD adwIsochLengths,
                      LPBOOL lpfComplete, LPDWORD lpdwBytesTransfered,
                      LPDWORD lpdwError);

BOOL HcdAbortTransfer(LPVOID lpvHcd, UINT iDevice, UINT iEndpointIndex,
                      LPTRANSFER_NOTIFY_ROUTINE lpStartAddress,
                      LPVOID lpvNotifyParameter, LPCVOID lpvCancelId);

}

#endif // _PHCD_HPP_