seg.mrp

multi-function clock

Release 6.1i Map G.23
Xilinx Mapping Report File for Design 'seg'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2v1000-fg456-6 -cm
area -pr b -k 4 -c 100 -tx off -o seg_map.ncd seg.ngd seg.pcf 
Target Device  : x2v1000
Target Package : fg456
Target Speed   : -6
Mapper Version : virtex2 -- $Revision: 1.16 $
Mapped Date    : Wed Dec 15 11:07:07 2004

Design Summary
--------------
Number of errors:      0
Number of warnings:    9
Logic Utilization:
  Total Number Slice Registers:        53 out of  10,240    1%
    Number used as Flip Flops:                    51
    Number used as Latches:                        2
  Number of 4 input LUTs:             132 out of  10,240    1%
Logic Distribution:
  Number of occupied Slices:           80 out of   5,120    1%
  Number of Slices containing only related logic:      80 out of      80  100%
  Number of Slices containing unrelated logic:          0 out of      80    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            150 out of  10,240    1%
  Number used as logic:               132
  Number used as a route-thru:         18

  Number of bonded IOBs:               20 out of     324    6%
  Number of GCLKs:                      1 out of      16    6%

Total equivalent gate count for design:  1,393
Additional JTAG gate count for IOBs:  960
Peak Memory Usage:  81 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net msecond10 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0023 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net second is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0024 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net hour is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net hour10 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net second10 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net minute is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net minute10 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| cs<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| cs<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| cs<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<0>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<1>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<2>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<3>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<4>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<5>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<6>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<7>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<0>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<1>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<2>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<3>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<4>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<5>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<6>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<7>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.