seg_map.mrp

multi-function clock

Release 8.1i Map I.24
Xilinx Mapping Report File for Design 'seg'

Design Information
------------------
Command Line   : D:\Xilinx\bin\nt\map.exe -ise E:/FPGA/Exp4-Clock/seg.ise
-intstyle ise -p xc2v1000-fg456-6 -cm area -pr b -k 4 -c 100 -tx off -o
seg_map.ncd seg.ngd seg.pcf 
Target Device  : xc2v1000
Target Package : fg456
Target Speed   : -6
Mapper Version : virtex2 -- $Revision: 1.34 $
Mapped Date    : Fri Jun 23 14:40:23 2006

Design Summary
--------------
Number of errors:      0
Number of warnings:    9
Logic Utilization:
  Total Number Slice Registers:        53 out of  10,240    1%
    Number used as Flip Flops:                    51
    Number used as Latches:                        2
  Number of 4 input LUTs:             132 out of  10,240    1%
Logic Distribution:
  Number of occupied Slices:           81 out of   5,120    1%
  Number of Slices containing only related logic:      81 out of      81  100%
  Number of Slices containing unrelated logic:          0 out of      81    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            150 out of  10,240    1%
  Number used as logic:               132
  Number used as a route-thru:         18

  Number of bonded IOBs:               20 out of     324    6%
  Number of GCLKs:                      1 out of      16    6%

Total equivalent gate count for design:  1,387
Additional JTAG gate count for IOBs:  960
Peak Memory Usage:  140 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:372 - Gated clock. Clock net minute10 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net msecond10 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net minute is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net second is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net hour is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net hour10 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net second10 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0021 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0022 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| cs<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| cs<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| cs<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<0>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<1>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<2>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<3>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<4>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<5>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<6>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg<7>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<0>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<1>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<2>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<3>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<4>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<5>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<6>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| seg_sel<7>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
--------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 20
Number of Equivalent Gates for Design = 1,387
Number of RPM Macros = 0
Number of Hard Macros = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
PCILOGICs = 0
DCMs = 0
GCLKs = 1
ICAPs = 0
18X18 Multipliers = 0
Block RAMs = 0
TBUFs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 29
IOB Dual-Rate Flops not driven by LUTs = 0
IOB Dual-Rate Flops = 0
IOB Slave Pads = 0
IOB Master Pads = 0
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 0
IOB Flip Flops = 0
Unbonded IOBs = 0
Bonded IOBs = 20
ORCYs = 0
XORs = 18
CARRY_INITs = 10
CARRY_SKIPs = 0
CARRY_MUXes = 18
Total Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MUXFs = 22
MULT_ANDs = 0
4 input LUTs used as Route-Thrus = 18
4 input LUTs = 132
Slice Latches not driven by LUTs = 2
Slice Latches = 2
Slice Flip Flops not driven by LUTs = 29
Slice Flip Flops = 51
Slices = 81
F6 Muxes = 7
F5 Muxes = 15
F8 Muxes = 0
F7 Muxes = 0
Number of LUT signals with 4 loads = 9
Number of LUT signals with 3 loads = 6
Number of LUT signals with 2 loads = 4
Number of LUT signals with 1 load = 112
NGM Average fanout of LUT = 1.48
NGM Maximum fanout of LUT = 22
NGM Average fanin for LUT = 3.4242
Number of LUT symbols = 132