xst.xmsgs

multi-function clock

<?xml version="1.0" encoding="UTF-8"?>
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<messages>
<msg type="warning" file="HDLParsers" num="3215" delta="unknown" >Unit <arg fmt="%s" index="1">work/seg</arg> is now defined in a different file: was <arg fmt="%s" index="2">E:/锞匡繂锟堬堪锟岋繕锞诧亢锟嗭痉/Create-SOPC锟忥镜锟侊繍/Create-SOPC1000X锟嗭粳锟夛繌锟忥镜锟嶏境锞斤繉锟戯晶锞匡惊锞凤劲锟嗭窘锟岋鲸/锟婏镜锟戯咯锞达亢锟傦揩/lab4/SEG.vhd</arg>, now is <arg fmt="%s" index="3">E:/FPGA/Exp4-Clock/SEG.vhd</arg>
</msg>

<msg type="warning" file="HDLParsers" num="3215" delta="unknown" >Unit <arg fmt="%s" index="1">work/seg/Behavioral</arg> is now defined in a different file: was <arg fmt="%s" index="2">E:/锞匡繂锟堬堪锟岋繕锞诧亢锟嗭痉/Create-SOPC锟忥镜锟侊繍/Create-SOPC1000X锟嗭粳锟夛繌锟忥镜锟嶏境锞斤繉锟戯晶锞匡惊锞凤劲锟嗭窘锟岋鲸/锟婏镜锟戯咯锞达亢锟傦揩/lab4/SEG.vhd</arg>, now is <arg fmt="%s" index="3">E:/FPGA/Exp4-Clock/SEG.vhd</arg>
</msg>

<msg type="warning" file="HDLParsers" num="3215" delta="unknown" >Unit <arg fmt="%s" index="1">work/count10</arg> is now defined in a different file: was <arg fmt="%s" index="2">E:/锞匡繂锟堬堪锟岋繕锞诧亢锟嗭痉/Create-SOPC锟忥镜锟侊繍/Create-SOPC1000X锟嗭粳锟夛繌锟忥镜锟嶏境锞斤繉锟戯晶锞匡惊锞凤劲锟嗭窘锟岋鲸/锟婏镜锟戯咯锞达亢锟傦揩/lab4/SEG.vhd</arg>, now is <arg fmt="%s" index="3">E:/FPGA/Exp4-Clock/SEG.vhd</arg>
</msg>

<msg type="warning" file="HDLParsers" num="3215" delta="unknown" >Unit <arg fmt="%s" index="1">work/count10/Behavioral</arg> is now defined in a different file: was <arg fmt="%s" index="2">E:/锞匡繂锟堬堪锟岋繕锞诧亢锟嗭痉/Create-SOPC锟忥镜锟侊繍/Create-SOPC1000X锟嗭粳锟夛繌锟忥镜锟嶏境锞斤繉锟戯晶锞匡惊锞凤劲锟嗭窘锟岋鲸/锟婏镜锟戯咯锞达亢锟傦揩/lab4/SEG.vhd</arg>, now is <arg fmt="%s" index="3">E:/FPGA/Exp4-Clock/SEG.vhd</arg>
</msg>

<msg type="warning" file="HDLParsers" num="3215" delta="unknown" >Unit <arg fmt="%s" index="1">work/count6</arg> is now defined in a different file: was <arg fmt="%s" index="2">E:/锞匡繂锟堬堪锟岋繕锞诧亢锟嗭痉/Create-SOPC锟忥镜锟侊繍/Create-SOPC1000X锟嗭粳锟夛繌锟忥镜锟嶏境锞斤繉锟戯晶锞匡惊锞凤劲锟嗭窘锟岋鲸/锟婏镜锟戯咯锞达亢锟傦揩/lab4/SEG.vhd</arg>, now is <arg fmt="%s" index="3">E:/FPGA/Exp4-Clock/SEG.vhd</arg>
</msg>

<msg type="warning" file="HDLParsers" num="3215" delta="unknown" >Unit <arg fmt="%s" index="1">work/count6/Behavioral</arg> is now defined in a different file: was <arg fmt="%s" index="2">E:/锞匡繂锟堬堪锟岋繕锞诧亢锟嗭痉/Create-SOPC锟忥镜锟侊繍/Create-SOPC1000X锟嗭粳锟夛繌锟忥镜锟嶏境锞斤繉锟戯晶锞匡惊锞凤劲锟嗭窘锟岋鲸/锟婏镜锟戯咯锞达亢锟傦揩/lab4/SEG.vhd</arg>, now is <arg fmt="%s" index="3">E:/FPGA/Exp4-Clock/SEG.vhd</arg>
</msg>

<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">297</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">328</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">297</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">328</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">297</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">328</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">297</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="info" file="Xst" num="1739" delta="unknown" >HDL ADVISOR - &quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">297</arg>: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
</msg>

<msg type="info" file="Xst" num="1561" delta="unknown" >&quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">277</arg>: Mux is complete : default of case is discarded
</msg>

<msg type="warning" file="Xst" num="819" delta="unknown" >&quot;<arg fmt="%s" index="1">E:/FPGA/Exp4-Clock/SEG.vhd</arg>&quot; line <arg fmt="%d" index="2">251</arg>: The following signals are missing in the process sensitivity list:
<arg fmt="%s" index="3">MsecSeg1, MsecSeg2, SecSeg1, SecSeg2, MinSeg1, MinSeg2, HourSeg1, HourSeg2</arg>.
</msg>

<msg type="warning" file="Xst" num="737" delta="unknown" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">HourSeg1_0</arg>&gt;.
</msg>

<msg type="info" file="Xst" num="2371" delta="unknown" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch.
</msg>

<msg type="warning" file="Xst" num="737" delta="unknown" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">MinSeg1_0</arg>&gt;.
</msg>

<msg type="info" file="Xst" num="2371" delta="unknown" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch.
</msg>

<msg type="info" file="Xst" num="2169" delta="unknown" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>

</messages>