📄 usb_to_serial.lst
字号:
0013= EP1_COUNT: equ 13h ; [R/W]
0015= EP2_COUNT: equ 15h ; [R/W]
0041= EP3_COUNT: equ 41h ; [R/W]
0043= EP4_COUNT: equ 43h ; [R/W]
;.............. Fields ....................................
0080= DATA_TOGGLE: equ 80h ; Data 0/1 bit
0040= DATA_VALID: equ 40h ; data valid (OUT and SETUP)
000F= CNT_MSK: equ 0Fh ; count[3:0] bits
;**********************************************************
; USB CONTROL AND STATUS REGISTER
;**********************************************************
; The USB Control and Status Register provides three
; functions. It allows for direct read of the D+/D- bits,
; it contains a flag indicating USB bus activity, and it
; provides the means for controlling the D+/D- bits
; directly.
;
; D+/D- control can be used for two different applications.
; Under normal operation, certain variations of the D+/D-
; bits are used to signal resume (remote wakeup) and USB
; reset. A variation can be implemented with the 4xx series
; of processors allowing the D+/D- pins to be connected to
; a PS/2 device rather than a USB device. In this mode,
; PS/2 support can be implemented via programmed I/O.
;**********************************************************
001F= USB_CTL: equ 1Fh ; [R/W]
;.............. Fields ....................................
; If USB_CTL[7:6] = [1,1], 5 Endpoint FIFOs, 2 are 32 Bytes, 3 are 8 Bytes.
; If USB_CTL[7:6] = [1,0], 3 Endpoint FIFOs, 2 are 32 Bytes, 3 are 8 Bytes.
; If USB_CTL[7:6] = [0,1], 5 Endpoint FIFOs, All are 8 Bytes
; If USB_CTL[7:6] = [0,0], 3 Endpoint FIFOs, All are 8 Bytes.
0080= EP_SIZE: equ 80h ; 8(0) or 32(1) byte FIFO
0040= EP_COUNT: equ 40h ; 0 = 3 EPs; 1 = 5 EPs
0030= D_BIT_MSK: equ 30h ; D+ and D-
0020= D_PLUS: equ 20h ; D+
0010= D_MINUS: equ 10h ; D-
0008= BUS_ACTIVE: equ 08h ; bus activity bit
0007= USB_CTL_MSK: equ 07h ; control[2:0] bits
; The following definitions select the assertion levels
; of the D+/D- bits of the USB pins. The nomenclature refers
; first to the forced state of D+ and then D-
0007= FORCE_HIZ_HIZ: equ 07h ; D+ HiZ, D- HiZ
0006= FORCE_LOW_HIZ: equ 06h ; D+ Low, D- HiZ
0005= FORCE_HIZ_LOW: equ 05h ; D+ HiZ, D- Low
0004= FORCE_SE0: equ 04h ; D+ Low, D- Low (SE0)
0004= FORCE_LOW_LOW: equ 04h ; D+ Low, D- Low (SE0)
; FORCE_LOW_LOW can be implemented via two values of the USB
; control. At this point, if needed, just use the 04h variant.
;FORCE_LOW_LOW: equ 03h ; D+ Low, D- Low (SE0)
0002= FORCE_J: equ 02h ; D+ Low, D- Hi
0002= FORCE_LOW_HI: equ 02h ; D+ Low, D- Hi
0001= FORCE_RESUME: equ 01h ; D+ Hi, D- Low (Resume)
0001= FORCE_K: equ 01h ; D+ Hi, D- Low (Resume)
0001= FORCE_HI_LOW: equ 01h ; D+ Hi, D- Low (Resume)
0000= FORCE_NONE: equ 00h ; SIE controls D+/D-
;**********************************************************
; USB ENDPOINT FIFOS
;**********************************************************
; The USB Endpoint FIFOs are actually located within
; the internal data memory space of the processor.
; NOTE: The CY7C64013 allows for two endpoint FIFOs to have
; selectable 8 or 32 byte sizes. Therefore two address
; schemes are used for all endpoints. If the 2 endpoints
; are 8 bytes then all endpoints will be of type A. If
; the 2 endpoints are 32 bytes then all endpoints will be
; of type B.
;**********************************************************
IF (FIFO_SIZE - 8) ; FIFO_SIZE is 32
00B8= ep0_fifo: equ B8h ; 8-byte FIFO
00C0= ep1_fifo: equ C0h ; 32-byte FIFO
00E0= ep2_fifo: equ E0h ; 32-byte FIFO
0008= SIZEOF_EP0_FIFO: equ 08h ; 8-byte FIFO
0020= SIZEOF_EP1_FIFO: equ 20h ; 32-byte FIFO
0020= SIZEOF_EP2_FIFO: equ 20h ; 32-byte FIFO
IF (NUM_EPS - 5) ; NUM_EPS is 3
00B7= TOP_OF_RAM: equ (ep0_fifo - 1) ;
ELSE ; NUM_EPS is 5
ENDIF
ENDIF
IF (FIFO_SIZE - 32) ; FIFO_SIZE is 8
IF (NUM_EPS - 5) ; NUM_EPS is 3
ELSE ; NUM_EPS is 5
ENDIF
ENDIF
;**********************************************************
; PROCESSOR CONTROL REGISTERS
;**********************************************************
;**********************************************************
; GLOBAL INTERRUPT ENABLE REGISTER
;**********************************************************
; The Global Interrupt Enable Register provides control
; over enabling/disabling particular interrupt sources. At
; reset, this register is cleared, disabling all interrupt
; sources.
;**********************************************************
0020= IE: equ 20h ; [R/W]
;.............. Fields ....................................
0040= I2C_INT_EN: equ 40h ; Enable I2C interrupt
0020= GPIO_INT_EN: equ 20h ; Enable GPIO interrupt
0010= DAC_INT_EN: equ 10h ; Enable DAC interrupt
0004= 1MS_INT_EN: equ 04h ; Enable 1 ms interrupt
0002= 128US_INT_EN: equ 02h ; Enable 128 us interrupt
0001= USB_RST_INT_EN: equ 01h ; Enable USB Reset interrupt
;**********************************************************
; ENDPOINT INTERRUPT ENABLE REGISTER
;**********************************************************
; The Endpoint Interrupt Enable Register provides control
; over enabling/disabling particular endpoint interrupt
; sources. At reset, this register is cleared, disabling
; all enpoint interrupts.
;**********************************************************
0021= EP_IE: equ 21h ; [R/W]
;.............. Fields ....................................
0010= EP4_IE: equ 10h ; Enable EP4 interrupt
0080= EP3_IE: equ 80h ; Enable EP3 interrupt
0004= EP2_IE: equ 04h ; Enable EP2 interrupt
0002= EP1_IE: equ 02h ; Enable EP1 interrupt
0001= EP0_IE: equ 01h ; Enable EP0 interrupt
;**********************************************************
; INTERRUPT VECTOR REGISTER
;**********************************************************
; The interrupt vector register contains the address of the
; highest priority pending interrupt. The value read
; from this register is only valid if the Global Interrupt
; bit has been disabled by the DI command, or if read during
; an ISR before re-enabling interrupts. i.e. reading 0x06
; from this register indicates the 1 ms timer interrupt.
;**********************************************************
0023= INT_VECT: equ 23h ; [R]
;**********************************************************
; TIMER REGISTER
;**********************************************************
; The Timer Register provides read-only access to a 12-bit
; free-running timer. When reading the full contents of the
; timer, the LSB should always be read first. This will
; latch the contents of the MSB for a subsequent read of
; the MSB latch.
;**********************************************************
0024= TMR_LSB: equ 24h ; [R]
0025= TMR_MSB: equ 25h ; [R]
;.............. Fields ....................................
003F= TMR_MSB_MSK: equ 3Fh ; six bits
;**********************************************************
; WATCHDOG TIMER REGISTER
;**********************************************************
; The Watchdog Timer Register provides a means for holding
; off a Watchdog Timer Reset. In order to prevent the WDT
; Reset from occurring, this register must be written (data
; = "don't care") at least every 8.192 ms.
;**********************************************************
0026= WDT: equ 26h ; [W]
;**********************************************************
; I2C CONTROL AND STATUS REGISTER
;**********************************************************
; The I2C Status and Control Register provides general
; control and status indication for an I2C transfer. This
; register should generally be monitored after an I2C
; interrupt, as all bits are valid at that time.
;
; NOTE: I2C Configurable Pins are set in the HAPI/I2C
; Configuration Register (0x09).
;**********************************************************
0028= I2C_CTL: equ 28h ; [R/W]
;.............. Fields ....................................
0080= MSTR_MODE: equ 80h ; Master Mode bit
0040= CNT_BUSY: equ 40h ; Continue/Busy bit
0020= XMIT_MODE: equ 20h ; Transmit Mode bit
0010= I2C_ACK: equ 10h ; ACK bit for Receive Mode
0008= I2C_ADDR: equ 08h ; Addr bit
0004= ARB: equ 04h ; Arbitration Lost/Restart bit
0002= RXD_STOP: equ 02h ; Received Stop bit
0001= I2C_EN: equ 01h ; I2C Enable bit
;**********************************************************
; I2C DATA REGISTER
;**********************************************************
; The I2C Data Register contains data to be read or written
; to the I2C port. This register is implemeted as seperate
; read and write registers.
;**********************************************************
0029= I2C_DATA: equ 29h ; [R/W]
;**********************************************************
; PROCESSOR CONTROL AND STATUS REGISTER
;**********************************************************
; The Processor Control and Status Register provides
; general control and status indication for the device. At
; POR reset, this register is set to 11h. During WDT reset,
; this register is set to 41h.
;**********************************************************
00FF= CTL: equ FFh ; [R/W]
;.............. Fields ....................................
0080= IRQ: equ 80h ; IRQ pending
0040= WDT_RST: equ 40h ; Watchdog Reset bit
0020= USB_RST: equ 20h ; USB Bus Reset bit
0010= POR: equ 10h ; power-on reset
0008= SUSP_EN: equ 08h ; Suspend, wait for interrupt
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -