📄 usb_to_serial.lst
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CYASM Version 1.96
(C) 1998,1999,2000,2001 Cypress Semiconductor Corp.
;****************************************************************
; FILE: USB_TO_SERIAL.ASM
;****************************************************************
0000 XPAGEON
;****************************************************************
; BUILD OPTIONS
;****************************************************************
; Uncomment one of the two following statements to
; select the target processor platform.
;**********************************************************
;
; 7C64013.INC
;
; Processor Hardware Definitions
;
; This file provides the constants associated with the
; Cypress 7C64013 USB processor.
;
;**********************************************************
0000 CPU 64013
;**********************************************************
; CONFIGURATION OPTIONS
;**********************************************************
; The 64013 provides support for either three or five
; endpoints. If five endpoints are required, uncomment
; the following line.
0003= NUM_EPS: equ 3 ;
;NUM_EPS: equ 5 ;
; The 64013 provides support for either 8- or 32-byte FIFOs.
; If 32-byte FIFOs are required, uncomment the following
; line.
;FIFO_SIZE: equ 8 ;
0020= FIFO_SIZE: equ 32 ;
;**********************************************************
; Processor Limitations
;**********************************************************
1FE0= ROM_SIZE: equ (8192 - 32) ;
0100= RAM_SIZE: equ 256 ;
0013= IO_SIZE: equ 19 ;
0002= HAPI_PORT: equ 2 ;
0001= I2C_PORT: equ 1 ;
;**********************************************************
; GPIO REGISTERS
;**********************************************************
;************** GPIO Data Registers ***********************
;
; The GPIO Data Ports provide control over each individual
; I/O bit. The GPIO Configuration Port (Pn_CFG) provides
; control over the mode of each I/O bit, configurable on a
; port basis.
;
; Ports 0 - 2 provide 7 mA sink current capability.
; Port 3 provides 12 mA sink current capability.
;
; At reset, all registers are set to FFh, configuring all
; data port pins as active high. The GPIO configuration
; register initializes all ports to resistive mode. In this
; configuration, all pins are passively pulling up the
; outputs.
;
;**********************************************************
0000= P0_DATA: equ 00h ; [R/W]
0001= P1_DATA: equ 01h ; [R/W]
0002= P2_DATA: equ 02h ; [R/W]
0003= P3_DATA: equ 03h ; [R/W]
;************** GPIO Interrupt Enables ********************
;
; The GPIO Interrupt Enable Register provides bit-level
; control over the generation of interrupts triggered by
; conditions on the GPIO data pins. A "1" written to a
; particular bit location enables interrupts on the
; corresponding data port bit location (i.e., When bit
; 2 of P0_IE is set to '1', interrupts are enabled
; on the input located at bit 2 of port 0 or P0.2).
;
; At reset, all registers are set to 00h, disabling all
; GPIO interrupt sources.
;
;**********************************************************
0004= P0_IE: equ 04h ; [W]
0005= P1_IE: equ 05h ; [W]
0006= P2_IE: equ 06h ; [W]
0007= P3_IE: equ 07h ; [W]
;************** GPIO Configuration Register ***************
;
; The GPIO Configuration Register controls the driving mode
; for each of the four GPIO data ports. Each port can be
; programmed as inputs with internal pull-ups, open-drain
; outputs or traditional CMOS outputs. Configuration is
; selected on a "by-port" basis. Two bits in each register
; control the driver mode for each data port.
;
; Value Driver Mode Interrupt Polarity
; ----- ----------- ------------------
; 00 Resistive Falling edge
; 01 CMOS No interrupts
; 10 Open Drain Falling edge
; 11 Open Drain Rising edge
;
; If driver mode is programmed to be CMOS (which does not
; support interrupts), the interrupt enable for each
; respective data port bit determines the direction (input
; or output) of that data port bit.
;
;**********************************************************
0008= GPIO_CFG: equ 08h ; [R/W]
;.............. Fields ....................................
0003= P0_CFG_MSK: equ 03h ;
000C= P1_CFG_MSK: equ 0Ch ;
0030= P2_CFG_MSK: equ 30h ;
00C0= P3_CFG_MSK: equ C0h ;
00FF= RES_NEG: equ FFh ;
00AA= CMOS_NONE: equ AAh ;
0055= OPEN_DRAIN_NEG: equ 55h ;
0000= OPEN_DRAIN_POS: equ 00h ;
;**********************************************************
; HAPI AND I2C CONFIGURATION REGISTER
;**********************************************************
; The HAPI and I2C Configuration Register contains three
; bits [7, 1:0] for controlling Pin configurations on each
; port. Bits [5:2] are used for HAPI mode only. All bits
; of this register are cleared on reset.
;**********************************************************
0009= HAPI_I2C: equ 09h ; [R/W]
;.............. Fields ....................................
0080= I2C_POSITION: equ 80h ; I2C Position bit
0020= LEMPTY_POL: equ 20h ; LEMPTY Polarity bit (HAPI)
0010= DRDY_POL: equ 10h ; DRDY Polarity bit (HAPI)
0008= LATCH_EMPTY: equ 08h ; Latch Empty bit (HAPI)
0004= DATA_RDY: equ 04h ; Data Ready bit (HAPI)
0002= PORT_WIDTH1: equ 02h ; Port Width bit 1
0001= PORT_WIDTH0: equ 01h ; Port Width bit 0
;**********************************************************
; USB REGISTERS
;**********************************************************
;**********************************************************
; USB ADDRESS REGISTER
;**********************************************************
; The USB Address Register contains the USB Address for the
; device. The USB interface will only respond to USB
; activity for a device at the address loaded into this
; register. At reset, this register is cleared, setting the
; address to zero and disabling the USB address.
;**********************************************************
0010= USB_ADDR: equ 10h ; [R/W]
;.............. Fields ....................................
0080= USB_ADDR_EN: equ 80h ; Enable the device address
; This bit must be set
; in order for the device
; to respond to USB activity.
007F= USB_ADDR_MSK: equ 7Fh ; 7 bits of device address
;**********************************************************
; ENDPOINT MODE REGISTERS
;**********************************************************
; The Endpoint Mode Registers control the USB operation for
; each of the specific endpoints. Endpoint 0 is a control
; endpoint and, as such, has additional controls available
; in the EP0_MODE. The endpoint mode registers are
; cleared on reset.
;**********************************************************
0012= EP0_MODE: equ 12h ; [R/W]
0014= EP1_MODE: equ 14h ; [R/W]
0016= EP2_MODE: equ 16h ; [R/W]
0042= EP3_MODE: equ 42h ; [R/W]
0044= EP4_MODE: equ 44h ; [R/W]
;.............. Fields ....................................
; Bits 7 - 5 are valid for endpoint 0 only
0080= SETUP_RXD: equ 80h ; EP0 SETUP received
0040= IN_RXD: equ 40h ; EP0 IN received
0020= OUT_RXD: equ 20h ; EP0 OUT received
; Bits 4-0 are valid for all endpoints
0010= ACKD: equ 10h ; ACK txd to or rxd from host
000F= MODE: equ 0Fh ; mode[3:0] bits
000F= ACK_IN_STATUS_OUT: equ 0Fh ; accept SETUP packets (EP zero)
000E= NAK_IN_STATUS_OUT: equ 0eh ;
000D= ACK_IN: equ 0Dh ; ACK IN packets (EP one)
000C= NAK_IN: equ 0Ch ; NAK IN packets
000B= ACK_OUT_STATUS_IN: equ 0Bh ; accept SETUP, TX0 IN, ACK OUT
000A= NAK_OUT_STATUS_IN: equ 0ah ;
0009= ACK_OUT: equ 09h ;
0008= NAK_OUT: equ 08h ;
0007= ISO_IN: equ 07h ;
0006= STATUS_IN_ONLY: equ 06h ; accept SETUP and IN (TX 0), stall OUT
0005= ISO_OUT: equ 05h ;
0004= IGNORE_IN_OUT: equ 04h ; accept SETUP packets
0003= STALL_IN_OUT: equ 03h ; stall IN and OUT packets
0002= STATUS_OUT_ONLY: equ 02h ; accept SETUP and OUT, stall IN
0001= NAK_IN_OUT: equ 01h ; accept SETUP, NAK IN and OUT
0000= DISABLED: equ 00h ; disabled
0004= SETUP_ONLY: equ IGNORE_IN_OUT ;
;**********************************************************
; ENDPOINT COUNT REGISTERS
;**********************************************************
; The Endpoint Count Registers provides control and status
; of the transfer count and data toggle of the previous/next
; transmission.
;**********************************************************
0011= EP0_COUNT: equ 11h ; [R/W]
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