7c63743.inc

usb serial converter

; the internal data memory space of the processor.
;**********************************************************

ep0_fifo:           equ     F8h             ; 8-byte FIFO
SIZEOF_EP0_FIFO:    equ     08h             ;

ep1_fifo:           equ     F0h             ; 8-byte FIFO
SIZEOF_EP1_FIFO:    equ     08h             ;

ep2_fifo:           equ     E8h             ; 8-byte FIFO
SIZEOF_EP2_FIFO:    equ     08h             ;

TOP_OF_RAM:         equ     (ep2_fifo - 1)  ;

;**********************************************************
; PROCESSOR CONTROL REGISTERS                  
;**********************************************************

;**********************************************************
; GLOBAL INTERRUPT ENABLE REGISTER
;**********************************************************
; The Global Interrupt Enable Register provides control 
; over enabling/disabling particular interrupt sources. At 
; reset, this register is cleared, disabling all interrupt 
; sources.
;**********************************************************

IE:                 equ     20h             ; [R/W]

;.............. Fields ....................................

WAKEUP_INT_EN:      equ     80h             ; Enable Wake-up interrupt
GPIO_INT_EN:        equ     40h             ; Enable GPIO interrupt
CAP_TMRA_INT_EN:    equ     20h             ; Enable Capture TimerA interrupt  
CAP_TMRB_INT_EN:    equ     10h             ; Enable Capture TimerB interrupt
SPI_INT_EN:         equ     08h             ; Enable SPI interrupt
1MS_INT_EN:         equ     04h             ; Enable 1 ms interrupt
128US_INT_EN:       equ     02h             ; Enable 128 us interrupt
USB_RST_INT_EN:     equ     01h             ; Enable USB Reset interrupt

;**********************************************************
; ENDPOINT INTERRUPT ENABLE REGISTER
;**********************************************************
; The Endpoint Interrupt Enable Register provides control 
; over enabling/disabling particular endpoint interrupt 
; sources. At reset, this register is cleared, disabling 
; all enpoint interrupts.
;**********************************************************

EP_IE:              equ     21h             ; [R/W]

;.............. Fields ....................................

EP2_IE:             equ     04h             ; Enable EP2 interrupt
EP1_IE:             equ     02h             ; Enable EP1 interrupt 
EP0_IE:             equ     01h             ; Enable EP0 interrupt

;**********************************************************
; TIMER REGISTER
;**********************************************************
; The Timer Register provides read-only access to a 12-bit
; free-running timer. When reading the full contents of the
; timer, the LSB should always be read first. This will 
; latch the contents of the MSB for a subsequent read of 
; the MSB latch.
;**********************************************************

TMR_LSB:            equ     24h             ; [R]
TMR_MSB:            equ     25h             ; [R]

;.............. Fields ....................................

TMR_MSB_MSK:        equ     3Fh             ; six bits

;**********************************************************
; WATCHDOG TIMER REGISTER
;**********************************************************
; The Watchdog Timer Register provides a means for holding 
; off a Watchdog Timer Reset. In order to prevent the WDT
; Reset from occurring, this register must be written (data 
; = "don't care") at least every 8.192 ms.
;**********************************************************

WDT:                equ     26h             ; [W]

;**********************************************************
; CAPTURE TIMER REGISTERS
;**********************************************************

;**********************************************************
; CAPTURE TIMER DATA REGISTERS
;**********************************************************
; The Capture Timer Data Registers contain an 8 bit value
; captured from the 12 bit free running timer. Upon a 
; rising or falling edge Capture Timer interrupt, a selectable
; 8 bits of the 12 bit free-running timer will be locked into
; the corresponding register. 
;**********************************************************

CAP_TMRA_RISE:      equ     40h             ; [R]
CAP_TMRA_FALL:      equ     41h             ; [R]

CAP_TMRB_RISE:      equ     42h             ; [R]
CAP_TMRB_FALL:      equ     43h             ; [R]

;**********************************************************
; CAPTURE TIMER CONFIGURATION REGISTER
;**********************************************************
; The Capture Timer Configuration Register contains 4 bits
; for enabling the Capture Timer interrupts.  It also has 3 
; prescale bits used to select among 5 capture clock rates
; along with the option for first edge holding. 
;
; Prescale [2:0]    Capture From    
;   000             7:0 of Free-Running Timer    
;   001             8:1 of Free-Running Timer     
;   010             9:2 of Free-Running Timer    
;   011             10:3 of Free-Running Timer
;   100             11:4 of Free-Running Timer
;**********************************************************

CAP_TMR_CFG:        equ     44h             ; [R/W]

;.............. Fields ....................................

FIRST_EDG_HOLD:     equ     80h             ; First Edge Hold bit
CAP_TMRB_FAL:       equ     08h             ; interrupt enable bit
CAP_TMRB_RIS:       equ     04h             ; interrupt enable bit
CAP_TMRA_FAL:       equ     02h             ; interrupt enable bit
CAP_TMRA_RIS:       equ     01h             ; interrupt enable bit

PRESCALE_MSK:       equ     70h             ; Prescale mask
 
;**********************************************************
; CAPTURE TIMER STATUS REGISTER
;**********************************************************
; The Capture Status Register records the occurrence of any
; rising or falling edges on the capture GPIO pins.  Bits
; in this register are cleared by reading the corresponding
; data register.
;**********************************************************

CAP_TMR_STAT:       equ     45h             ; [R]

;**********************************************************
; SPI REGISTERS
;**********************************************************

;**********************************************************
; SPI DATA REGISTER
;**********************************************************
; The SPI Data Register contains data transmitted or received
; on the SPI port.  Writes to the SPI Data Register load the
; transmit buffer, while reads from this regiter read the
; received byffer contents.
;**********************************************************

SPI_DATA:           equ     60h             ; [R/W]

;**********************************************************
; SPI CONTROL REGISTER
;**********************************************************
; The SPI Status and Control Register allows for SPI Clock
; configuration and Master/Slave mode selection.  It also
; and two status bits TBF and TCMP, that signal respectively 
; that the transmit buffer is full and that a transfer is complete.
;**********************************************************

SPI_CNT:            equ     61h             ; [R/W]

;.............. Fields ....................................

TCMP:               equ     80h             ; Transfer Complete bit
TBF:                equ     40h             ; Transmit Buffer Full bit
CPOL:               equ     08h             ; Clock Parity bit
CPHA:               equ     04h             ; Clock Phase bit

SPI_MODE_MSK:       equ     30h             ; Communication mode mask
SPI_SCK_MSK:        equ     03h             ; SCK mask

;**********************************************************
; CLOCK CONFIGURATION REGISTER
;**********************************************************
; The Clock Configuration Register provides options for 
; internal and external clocking, wake-up timer period, and
; Low voltage reset disable.
;
; All bits are set to "0" on reset. 
;**********************************************************

CLK_CFG:            equ     F8h             ; Clock Configuration

;.............. Fields ....................................

RESUME_DELAY:       equ     80h             ; Ext. Clock Resume Delay bit
WAKEUP_TMR_ADJ2:    equ     40h             ; Wake-up Timer Adjust bit2
WAKEUP_TMR_ADJ1:    equ     20h             ; Wake-up Timer Adjust bit1
WAKEUP_TMR_ADJ0:    equ     10h             ; Wake-up Timer Adjust bit0
LVR_DISABLE:        equ     08h             ; Low Voltage Reset bit
PRECISION_CLK_EN:   equ     04h             ; Precision Clocking Enable bit
INT_CLK_OUTPUT:     equ     02h             ; Internal Clock Output Disable bit
EXT_OSC_EN:         equ     01h             ; External Oscillator Enable

;**********************************************************
; PROCESSOR CONTROL AND STATUS REGISTER
;**********************************************************
; The Processor Control and Status Register provides 
; general control and status indication for the device. At 
; POR reset, this register is set to 11h. During WDT reset,
; this register is set to 41h.
;**********************************************************

CTL:                equ     FFh             ; [R/W]

;.............. Fields ....................................

IRQ:                equ     80h             ; IRQ pending
WDT_RST:            equ     40h             ; Watchdog Reset bit
USB_RST:            equ     20h             ; USB Bus Reset bit
POR:                equ     10h             ; power-on reset
SUSP_EN:            equ     08h             ; Suspend, wait for interrupt
INT_EN:             equ     04h             ; interrupt enable
RUN_EN:             equ     01h             ; CPU Run bit

;**********************************************************
; INTERRUPT VECTOR TABLE
;**********************************************************

MACRO INTERRUPT_VECTOR_TABLE

XPAGEOFF

    jmp     Reset_Isr                       ;
    jmp     Bus_Reset_Isr                   ;
    jmp     128us_Isr                       ;
    jmp     1ms_Isr                         ;
    jmp     Ep0_Isr                         ;
    jmp     Ep1_Isr                         ;
    jmp     Ep2_Isr                         ;
    jmp     Spi_Isr                         ;
    jmp     Capture_A_Isr                   ;
    jmp     Capture_B_Isr                   ;
    jmp     Gpio_Isr                        ;
    jmp     Wakeup_Isr                      ;

XPAGEON

ENDM