7c63743.inc

usb serial converter

;**********************************************************
; 7C63743.INC
; Processor Hardware Definitions
;
; This file provides the constants associated with the 
; Cypress 7C63743 USB processor.
;**********************************************************

CPU 63743

NUM_EPS:            equ     3               ;
FIFO_SIZE:          equ     8               ;

;**********************************************************
; Processor Limitations
;**********************************************************

ROM_SIZE:           equ     (8192 - 32)     ;
RAM_SIZE:           equ     256             ;

IO_SIZE:            equ     16              ;                   //MUL, PORT equ relate to port #, not # of ports
SPI_PORT:           equ     0               ;

;**********************************************************
; GPIO REGISTERS
;**********************************************************

;**********************************************************
; GPIO DATA REGISTERS
;**********************************************************
; The GPIO Data Registers along with the GPIO Port Mode
; Registers together determine the charateristics of each
; GPIO port pins.  The Data Registers ultimately determine
; whether the GPIO pin is in one of three states:
; 
; 1) Sink  2) Source  3) Hi-Z.
; 
; Ports 0 - 1 provide 50 mA sink current capability.
;
; At reset, all registers are set to FFh, configuring all         //MUL, I'm skeptical of this statement.
; data port pins as active high. The GPIO configuration 
; register initializes all ports to resistive mode. In this
; configuration, all pins are passively pulling up the 
; outputs.
;**********************************************************

P0_DATA:            equ     00h             ; [R/W]
P1_DATA:            equ     01h             ; [R/W]
P2_DATA:            equ     02h             ; [R]

;**********************************************************
; GPIO INTERRUPT ENABLE REGISTERS
;**********************************************************
; The GPIO Interrupt Enable Registers provides bit-level 
; control over the generation of interrupts triggered by
; conditions on the GPIO data pins. A "1" written to a 
; particular bit location enables interrupts on the 
; corresponding data port bit location (i.e., When bit
; 2 of P0_IE is set to '1', interrupts are enabled
; on the input located at bit 2 of port 0 or P0.2).
;
; At reset, all registers are set to 00h, disabling all 
; GPIO interrupt sources.
;**********************************************************

P0_IE:              equ     04h             ; [W]
P1_IE:              equ     05h             ; [W]

;**********************************************************
; GPIO INTERRUPT POLARITY REGISTER
;**********************************************************
; The GPIO Interrupt Enable Polarity provides bit-level
; control over rising-edge, or falling-edge triggered
; interrupts.  A "1" wrtten to a particular bit location
; sets the mode to rising-edge for the corresponding GPIO 
; pin.  Conversely, a "0" sets the mode to falling-edge.
;
; At reset, this register resets to 00h, or falling-edge.
;**********************************************************

P0_IP:              equ     06h             ; [W]
P1_IP:              equ     07h             ; [W]  

;**********************************************************
; GPIO PORT MODE REGISTERS
;**********************************************************
; The GPIO Port Mode Registers along with the GPIO Data 
; Registers, together determine the charateristics of each
; GPIO port pin.
;
; MODE [1,0]  
;  00               Hi-Z Mode.
;  01               Medium Drive CMOS Mode.
;  10               Low Drive/Resistive Mode.
;  11               High Drive CMOS Mode.
;**********************************************************

P0_MODE_0:          equ     0Ah             ;
P0_MODE_1:          equ     0Bh             ;

P1_MODE_0:          equ     0Ch             ;
P1_MODE_1:          equ     0Dh             ;

;**********************************************************
; USB REGISTERS                      
;**********************************************************

;**********************************************************
; USB ADDRESS REGISTER
;**********************************************************
; The USB Address Register contains the USB Address for the
; device. The USB interface will only respond to USB 
; activity for a device at the address loaded into this
; register. At reset, this register is cleared, setting the 
; address to zero and disabling the USB address. 
;**********************************************************

USB_ADDR:           equ     10h             ; [R/W]

;.............. Fields ....................................

USB_ADDR_EN:        equ     80h             ; Enable the device address
                                            ; This bit must be set
                                            ; in order for the device
                                            ; to respond to USB activity.

USB_ADDR_MSK:       equ     7Fh             ; 7 bits of device address

;**********************************************************
; ENDPOINT MODE REGISTERS
;**********************************************************
; The Endpoint Mode Registers control the USB operation for
; each of the specific endpoints. Endpoint 0 is a control 
; endpoint and, as such, has additional controls available 
; in the EP0_MODE. The endpoint mode registers are 
; cleared on reset.
;**********************************************************

EP0_MODE:           equ     12h             ; [R/W]
EP1_MODE:           equ     14h             ; [R/W]
EP2_MODE:           equ     16h             ; [R/W]

;.............. Fields ....................................

; Bits 7 - 5 are valid for endpoint 0 only

SETUP_RXD:          equ     80h             ; EP0 SETUP received
IN_RXD:             equ     40h             ; EP0 IN received
OUT_RXD:            equ     20h             ; EP0 OUT received

; Bits 4-0 are valid for all endpoints

ACKD:               equ     10h             ; ACK txd to or rxd from host

MODE:               equ     0Fh             ; mode[3:0] bits

ACK_IN_STATUS_OUT:  equ     0Fh             ; accept SETUP packets (EP zero) 
NAK_IN_STATUS_OUT:  equ     0eh             ;
ACK_IN:             equ     0Dh             ; ACK IN packets (EP one)
NAK_IN:             equ     0Ch             ; NAK IN packets
ACK_OUT_STATUS_IN:  equ     0Bh             ; accept SETUP, TX0 IN, ACK OUT
NAK_OUT_STATUS_IN:  equ     0ah             ;
ACK_OUT:            equ     09h             ;
NAK_OUT:            equ     08h             ;
ISO_IN:             equ     07h             ;
STATUS_IN_ONLY:     equ     06h             ; accept SETUP and IN (TX 0), stall OUT
ISO_OUT:            equ     05h             ;
IGNORE_IN_OUT:      equ     04h             ; accept SETUP packets
STALL_IN_OUT:       equ     03h             ; stall IN and OUT packets
STATUS_OUT_ONLY:    equ     02h             ; accept SETUP and OUT, stall IN
NAK_IN_OUT:         equ     01h             ; accept SETUP, NAK IN and OUT
DISABLED:           equ     00h             ; disabled

SETUP_ONLY:         equ     IGNORE_IN_OUT   ;

;**********************************************************
; ENDPOINT COUNT REGISTERS
;**********************************************************
; The Endpoint Count Registers provides control and status 
; of the transfer count and data toggle of the previous/next
; transmission.
;**********************************************************

EP0_COUNT:          equ     11h             ; [R/W]
EP1_COUNT:          equ     13h             ; [R/W]
EP2_COUNT:          equ     15h             ; [R/W]

;.............. Fields ....................................

DATA_TOGGLE:        equ     80h             ; Data 0/1 bit
DATA_VALID:         equ     40h             ; data valid (OUT and SETUP)
CNT_MSK:            equ     0fh             ; count[3:0] bits

;**********************************************************
; USB CONTROL AND STATUS REGISTER
;**********************************************************
; The USB Control and Status Register provides three 
; functions. It allows for direct read of the D+/D- bits,
; it contains a flag indicating USB bus activity, and it
; provides the means for controlling the D+/D- bits 
; directly. 
;
; D+/D- control can be used for two different applications. 
; Under normal operation, certain variations of the D+/D-
; bits are used to signal resume (remote wakeup) and USB
; reset. A variation can be implemented with the 4xx series
; of processors allowing the D+/D- pins to be connected to
; a PS/2 device rather than a USB device. In this mode,
; PS/2 support can be implemented via programmed I/O.
;**********************************************************

USB_CTL:            equ     1Fh             ; [R/W]

;.............. Fields ....................................

PS2_EN:             equ     80h             ; PS2 Pull-Up Enable bit
VREG_EN:            equ     40h             ; VREG Enable bit
RST_ACT_MODE:       equ     20h             ; USB Reset-PS/2 Activity- 
                                            ; Interrupt Mode bit
BUS_ACTIVE:         equ     08h             ; bus activity bit
USB_CTL_MSK:        equ     07h             ; control[2:0] bits

; The following definitions select the assertion levels
; of the D+/D- bits of the USB pins. The nomenclature refers
; first to the forced state of D+ and then D-

FORCE_HIZ_HIZ:      equ     07h             ; D+ HiZ, D- HiZ
FORCE_LOW_HIZ:      equ     06h             ; D+ Low, D- HiZ
FORCE_HIZ_LOW:      equ     05h             ; D+ HiZ, D- Low

FORCE_SE0:          equ     04h             ; D+ Low, D- Low (SE0)
FORCE_LOW_LOW:      equ     04h             ; D+ Low, D- Low (SE0)

; FORCE_LOW_LOW can be implemented via two values of the USB
; control. At this point, if needed, just use the 04h variant.

;FORCE_LOW_LOW:     equ     03h             ; D+ Low, D- Low (SE0)

FORCE_J:            equ     02h             ; D+ Low, D- Hi
FORCE_LOW_HI:       equ     02h             ; D+ Low, D- Hi

FORCE_RESUME:       equ     01h             ; D+ Hi, D- Low (Resume)
FORCE_K:            equ     01h             ; D+ Hi, D- Low (Resume)
FORCE_HI_LOW:       equ     01h             ; D+ Hi, D- Low (Resume)

FORCE_NONE:         equ     00h             ; SIE controls D+/D-

;**********************************************************
; USB ENDPOINT FIFOS
;**********************************************************
; The USB Endpoint FIFOs are actually located within