📄 7c64013.inc
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D_BIT_MSK: equ 30h ; D+ and D-
D_PLUS: equ 20h ; D+
D_MINUS: equ 10h ; D-
BUS_ACTIVE: equ 08h ; bus activity bit
USB_CTL_MSK: equ 07h ; control[2:0] bits
; The following definitions select the assertion levels
; of the D+/D- bits of the USB pins. The nomenclature refers
; first to the forced state of D+ and then D-
FORCE_HIZ_HIZ: equ 07h ; D+ HiZ, D- HiZ
FORCE_LOW_HIZ: equ 06h ; D+ Low, D- HiZ
FORCE_HIZ_LOW: equ 05h ; D+ HiZ, D- Low
FORCE_SE0: equ 04h ; D+ Low, D- Low (SE0)
FORCE_LOW_LOW: equ 04h ; D+ Low, D- Low (SE0)
; FORCE_LOW_LOW can be implemented via two values of the USB
; control. At this point, if needed, just use the 04h variant.
;FORCE_LOW_LOW: equ 03h ; D+ Low, D- Low (SE0)
FORCE_J: equ 02h ; D+ Low, D- Hi
FORCE_LOW_HI: equ 02h ; D+ Low, D- Hi
FORCE_RESUME: equ 01h ; D+ Hi, D- Low (Resume)
FORCE_K: equ 01h ; D+ Hi, D- Low (Resume)
FORCE_HI_LOW: equ 01h ; D+ Hi, D- Low (Resume)
FORCE_NONE: equ 00h ; SIE controls D+/D-
;**********************************************************
; USB ENDPOINT FIFOS
;**********************************************************
; The USB Endpoint FIFOs are actually located within
; the internal data memory space of the processor.
; NOTE: The CY7C64013 allows for two endpoint FIFOs to have
; selectable 8 or 32 byte sizes. Therefore two address
; schemes are used for all endpoints. If the 2 endpoints
; are 8 bytes then all endpoints will be of type A. If
; the 2 endpoints are 32 bytes then all endpoints will be
; of type B.
;**********************************************************
IF (FIFO_SIZE - 8) ; FIFO_SIZE is 32
ep0_fifo: equ B8h ; 8-byte FIFO
ep1_fifo: equ C0h ; 32-byte FIFO
ep2_fifo: equ E0h ; 32-byte FIFO
SIZEOF_EP0_FIFO: equ 08h ; 8-byte FIFO
SIZEOF_EP1_FIFO: equ 20h ; 32-byte FIFO
SIZEOF_EP2_FIFO: equ 20h ; 32-byte FIFO
IF (NUM_EPS - 5) ; NUM_EPS is 3
TOP_OF_RAM: equ (ep0_fifo - 1) ;
ELSE ; NUM_EPS is 5
TOP_OF_RAM: equ (ep3_fifo - 1) ;
ep3_fifo: equ A8h ; 8-byte FIFO
ep4_fifo: equ B0h ; 8-byte FIFO
SIZEOF_EP3_FIFO: equ 08h ; 8-byte FIFO
SIZEOF_EP4_FIF0: equ 08h ; 8-byte FIFO
ENDIF
ENDIF
IF (FIFO_SIZE - 32) ; FIFO_SIZE is 8
ep0_fifo: equ F8h ; 8-byte FIFO
ep1_fifo: equ F0h ; 8-byte FIFO
ep2_fifo: equ E8h ; 8-byte FIFO
SIZEOF_EP0_FIFO: equ 08h ; 8-byte FIFO
SIZEOF_EP1_FIFO: equ 08h ; 8-byte FIFO
SIZEOF_EP2_FIFO: equ 08h ; 8-byte FIFO
IF (NUM_EPS - 5) ; NUM_EPS is 3
TOP_OF_RAM: equ (ep2_fifo - 1) ;
ELSE ; NUM_EPS is 5
TOP_OF_RAM: equ (ep4_fifo - 1) ;
ep3_fifo: equ E0h ; 8-byte FIFO
ep4_fifo: equ D8h ; 8-byte FIFO
SIZEOF_EP3_FIFO: equ 08h ; 8-byte FIFO
SIZEOF_EP4_FIF0: equ 08h ; 8-byte FIFO
ENDIF
ENDIF
;**********************************************************
; PROCESSOR CONTROL REGISTERS
;**********************************************************
;**********************************************************
; GLOBAL INTERRUPT ENABLE REGISTER
;**********************************************************
; The Global Interrupt Enable Register provides control
; over enabling/disabling particular interrupt sources. At
; reset, this register is cleared, disabling all interrupt
; sources.
;**********************************************************
IE: equ 20h ; [R/W]
;.............. Fields ....................................
I2C_INT_EN: equ 40h ; Enable I2C interrupt
GPIO_INT_EN: equ 20h ; Enable GPIO interrupt
DAC_INT_EN: equ 10h ; Enable DAC interrupt
1MS_INT_EN: equ 04h ; Enable 1 ms interrupt
128US_INT_EN: equ 02h ; Enable 128 us interrupt
USB_RST_INT_EN: equ 01h ; Enable USB Reset interrupt
;**********************************************************
; ENDPOINT INTERRUPT ENABLE REGISTER
;**********************************************************
; The Endpoint Interrupt Enable Register provides control
; over enabling/disabling particular endpoint interrupt
; sources. At reset, this register is cleared, disabling
; all enpoint interrupts.
;**********************************************************
EP_IE: equ 21h ; [R/W]
;.............. Fields ....................................
EP4_IE: equ 10h ; Enable EP4 interrupt
EP3_IE: equ 80h ; Enable EP3 interrupt
EP2_IE: equ 04h ; Enable EP2 interrupt
EP1_IE: equ 02h ; Enable EP1 interrupt
EP0_IE: equ 01h ; Enable EP0 interrupt
;**********************************************************
; INTERRUPT VECTOR REGISTER
;**********************************************************
; The interrupt vector register contains the address of the
; highest priority pending interrupt. The value read
; from this register is only valid if the Global Interrupt
; bit has been disabled by the DI command, or if read during
; an ISR before re-enabling interrupts. i.e. reading 0x06
; from this register indicates the 1 ms timer interrupt.
;**********************************************************
INT_VECT: equ 23h ; [R]
;**********************************************************
; TIMER REGISTER
;**********************************************************
; The Timer Register provides read-only access to a 12-bit
; free-running timer. When reading the full contents of the
; timer, the LSB should always be read first. This will
; latch the contents of the MSB for a subsequent read of
; the MSB latch.
;**********************************************************
TMR_LSB: equ 24h ; [R]
TMR_MSB: equ 25h ; [R]
;.............. Fields ....................................
TMR_MSB_MSK: equ 3Fh ; six bits
;**********************************************************
; WATCHDOG TIMER REGISTER
;**********************************************************
; The Watchdog Timer Register provides a means for holding
; off a Watchdog Timer Reset. In order to prevent the WDT
; Reset from occurring, this register must be written (data
; = "don't care") at least every 8.192 ms.
;**********************************************************
WDT: equ 26h ; [W]
;**********************************************************
; I2C CONTROL AND STATUS REGISTER
;**********************************************************
; The I2C Status and Control Register provides general
; control and status indication for an I2C transfer. This
; register should generally be monitored after an I2C
; interrupt, as all bits are valid at that time.
;
; NOTE: I2C Configurable Pins are set in the HAPI/I2C
; Configuration Register (0x09).
;**********************************************************
I2C_CTL: equ 28h ; [R/W]
;.............. Fields ....................................
MSTR_MODE: equ 80h ; Master Mode bit
CNT_BUSY: equ 40h ; Continue/Busy bit
XMIT_MODE: equ 20h ; Transmit Mode bit
I2C_ACK: equ 10h ; ACK bit for Receive Mode
I2C_ADDR: equ 08h ; Addr bit
ARB: equ 04h ; Arbitration Lost/Restart bit
RXD_STOP: equ 02h ; Received Stop bit
I2C_EN: equ 01h ; I2C Enable bit
;**********************************************************
; I2C DATA REGISTER
;**********************************************************
; The I2C Data Register contains data to be read or written
; to the I2C port. This register is implemeted as seperate
; read and write registers.
;**********************************************************
I2C_DATA: equ 29h ; [R/W]
;**********************************************************
; PROCESSOR CONTROL AND STATUS REGISTER
;**********************************************************
; The Processor Control and Status Register provides
; general control and status indication for the device. At
; POR reset, this register is set to 11h. During WDT reset,
; this register is set to 41h.
;**********************************************************
CTL: equ FFh ; [R/W]
;.............. Fields ....................................
IRQ: equ 80h ; IRQ pending
WDT_RST: equ 40h ; Watchdog Reset bit
USB_RST: equ 20h ; USB Bus Reset bit
POR: equ 10h ; power-on reset
SUSP_EN: equ 08h ; Suspend, wait for interrupt
INT_EN: equ 04h ; interrupt enable
SS_EN: equ 02h ; Single Step
RUN_EN: equ 01h ; CPU Run bit
;**********************************************************
; INTERRUPT VECTOR TABLE
;**********************************************************
MACRO INTERRUPT_VECTOR_TABLE
XPAGEOFF
jmp Reset_Isr ;
jmp Bus_Reset_Isr ;
jmp 128us_Isr ;
jmp 1ms_Isr ;
jmp Ep0_Isr ;
jmp Ep1_Isr ;
jmp Ep2_Isr ;
jmp Ep3_Isr ;
jmp Ep4_Isr ;
jmp Reserved_Isr ;
jmp Dac_Isr ;
jmp Gpio_Isr ;
jmp I2c_Isr ;
XPAGEON
ENDM
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