7c64013.inc

usb serial converter

;**********************************************************
;
; 7C64013.INC
;
; Processor Hardware Definitions
;
; This file provides the constants associated with the 
; Cypress 7C64013 USB processor.
;
;**********************************************************

CPU 64013

;**********************************************************
; CONFIGURATION OPTIONS
;**********************************************************

; The 64013 provides support for either three or five 
; endpoints. If five endpoints are required, uncomment
; the following line.

NUM_EPS:            equ     3               ;
;NUM_EPS:           equ     5               ;

; The 64013 provides support for either 8- or 32-byte FIFOs. 
; If 32-byte FIFOs are required, uncomment the following 
; line.

;FIFO_SIZE:         equ     8               ;
FIFO_SIZE:          equ     32              ;

;**********************************************************
; Processor Limitations
;**********************************************************

ROM_SIZE:           equ     (8192 - 32)     ;
RAM_SIZE:           equ     256             ;

IO_SIZE:            equ     19              ;
HAPI_PORT:          equ     2               ;
I2C_PORT:           equ     1               ;

;**********************************************************
; GPIO REGISTERS
;**********************************************************

;************** GPIO Data Registers ***********************
;
; The GPIO Data Ports provide control over each individual
; I/O bit. The GPIO Configuration Port (Pn_CFG) provides
; control over the mode of each I/O bit, configurable on a
; port basis. 
;
; Ports 0 - 2 provide 7 mA sink current capability.
; Port 3 provides 12 mA sink current capability. 
;
; At reset, all registers are set to FFh, configuring all
; data port pins as active high. The GPIO configuration 
; register initializes all ports to resistive mode. In this
; configuration, all pins are passively pulling up the 
; outputs.
;
;**********************************************************

P0_DATA:            equ     00h             ; [R/W]
P1_DATA:            equ     01h             ; [R/W]
P2_DATA:            equ     02h             ; [R/W]
P3_DATA:            equ     03h             ; [R/W]

;************** GPIO Interrupt Enables ********************
;
; The GPIO Interrupt Enable Register provides bit-level 
; control over the generation of interrupts triggered by
; conditions on the GPIO data pins. A "1" written to a 
; particular bit location enables interrupts on the 
; corresponding data port bit location (i.e., When bit
; 2 of P0_IE is set to '1', interrupts are enabled
; on the input located at bit 2 of port 0 or P0.2).
;
; At reset, all registers are set to 00h, disabling all 
; GPIO interrupt sources.
;
;**********************************************************

P0_IE:              equ     04h             ; [W]
P1_IE:              equ     05h             ; [W]
P2_IE:              equ     06h             ; [W]
P3_IE:              equ     07h             ; [W]
        
;************** GPIO Configuration Register ***************
;
; The GPIO Configuration Register controls the driving mode
; for each of the four GPIO data ports. Each port can be 
; programmed as inputs with internal pull-ups, open-drain
; outputs or traditional CMOS outputs. Configuration is 
; selected on a "by-port" basis. Two bits in each register
; control the driver mode for each data port.
;
; Value Driver Mode Interrupt Polarity
; ----- ----------- ------------------
; 00    Resistive   Falling edge
; 01    CMOS        No interrupts
; 10    Open Drain  Falling edge
; 11    Open Drain  Rising edge
;
; If driver mode is programmed to be CMOS (which does not
; support interrupts), the interrupt enable for each 
; respective data port bit determines the direction (input
; or output) of that data port bit.
;
;**********************************************************

GPIO_CFG:           equ     08h             ; [R/W] 

;.............. Fields ....................................

P0_CFG_MSK:         equ     03h             ;
P1_CFG_MSK:         equ     0Ch             ;
P2_CFG_MSK:         equ     30h             ;
P3_CFG_MSK:         equ     C0h             ;

RES_NEG:            equ     FFh             ;
CMOS_NONE:          equ     AAh             ;
OPEN_DRAIN_NEG:     equ     55h             ;
OPEN_DRAIN_POS:     equ     00h             ;

;**********************************************************
; HAPI AND I2C CONFIGURATION REGISTER
;**********************************************************
; The HAPI and I2C Configuration Register contains three
; bits [7, 1:0] for controlling Pin configurations on each 
; port.  Bits [5:2] are used for HAPI mode only.  All bits
; of this register are cleared on reset.
;**********************************************************

HAPI_I2C:           equ     09h             ; [R/W]

;.............. Fields ....................................

I2C_POSITION:       equ     80h             ; I2C Position bit
LEMPTY_POL:         equ     20h             ; LEMPTY Polarity bit (HAPI)
DRDY_POL:           equ     10h             ; DRDY Polarity bit (HAPI)
LATCH_EMPTY:        equ     08h             ; Latch Empty bit (HAPI)
DATA_RDY:           equ     04h             ; Data Ready bit (HAPI)
PORT_WIDTH1:        equ     02h             ; Port Width bit 1
PORT_WIDTH0:        equ     01h             ; Port Width bit 0

;**********************************************************
; USB REGISTERS                      
;**********************************************************

;**********************************************************
; USB ADDRESS REGISTER
;**********************************************************
; The USB Address Register contains the USB Address for the
; device. The USB interface will only respond to USB 
; activity for a device at the address loaded into this
; register. At reset, this register is cleared, setting the 
; address to zero and disabling the USB address. 
;**********************************************************

USB_ADDR:           equ     10h             ; [R/W]

;.............. Fields ....................................

USB_ADDR_EN:        equ     80h             ; Enable the device address
                                            ; This bit must be set
                                            ; in order for the device
                                            ; to respond to USB activity.

USB_ADDR_MSK:       equ     7Fh             ; 7 bits of device address

;**********************************************************
; ENDPOINT MODE REGISTERS
;**********************************************************
; The Endpoint Mode Registers control the USB operation for
; each of the specific endpoints. Endpoint 0 is a control 
; endpoint and, as such, has additional controls available 
; in the EP0_MODE. The endpoint mode registers are 
; cleared on reset.
;**********************************************************

EP0_MODE:           equ     12h             ; [R/W]
EP1_MODE:           equ     14h             ; [R/W]
EP2_MODE:           equ     16h             ; [R/W]
EP3_MODE:           equ     42h             ; [R/W]
EP4_MODE:           equ     44h             ; [R/W]

;.............. Fields ....................................

; Bits 7 - 5 are valid for endpoint 0 only

SETUP_RXD:          equ     80h             ; EP0 SETUP received
IN_RXD:             equ     40h             ; EP0 IN received
OUT_RXD:            equ     20h             ; EP0 OUT received

; Bits 4-0 are valid for all endpoints

ACKD:               equ     10h             ; ACK txd to or rxd from host

MODE:               equ     0Fh             ; mode[3:0] bits

ACK_IN_STATUS_OUT:  equ     0Fh             ; accept SETUP packets (EP zero) 
NAK_IN_STATUS_OUT:  equ     0eh             ;
ACK_IN:             equ     0Dh             ; ACK IN packets (EP one)
NAK_IN:             equ     0Ch             ; NAK IN packets
ACK_OUT_STATUS_IN:  equ     0Bh             ; accept SETUP, TX0 IN, ACK OUT
NAK_OUT_STATUS_IN:  equ     0ah             ;
ACK_OUT:            equ     09h             ;
NAK_OUT:            equ     08h             ;
ISO_IN:             equ     07h             ;
STATUS_IN_ONLY:     equ     06h             ; accept SETUP and IN (TX 0), stall OUT
ISO_OUT:            equ     05h             ;
IGNORE_IN_OUT:      equ     04h             ; accept SETUP packets
STALL_IN_OUT:       equ     03h             ; stall IN and OUT packets
STATUS_OUT_ONLY:    equ     02h             ; accept SETUP and OUT, stall IN
NAK_IN_OUT:         equ     01h             ; accept SETUP, NAK IN and OUT
DISABLED:           equ     00h             ; disabled

SETUP_ONLY:         equ     IGNORE_IN_OUT   ;

;**********************************************************
; ENDPOINT COUNT REGISTERS
;**********************************************************
; The Endpoint Count Registers provides control and status 
; of the transfer count and data toggle of the previous/next
; transmission.
;**********************************************************

EP0_COUNT:          equ     11h             ; [R/W]
EP1_COUNT:          equ     13h             ; [R/W]
EP2_COUNT:          equ     15h             ; [R/W]
EP3_COUNT:          equ     41h             ; [R/W]
EP4_COUNT:          equ     43h             ; [R/W]

;.............. Fields ....................................

DATA_TOGGLE:        equ     80h             ; Data 0/1 bit
DATA_VALID:         equ     40h             ; data valid (OUT and SETUP)
CNT_MSK:            equ     0Fh             ; count[3:0] bits

;**********************************************************
; USB CONTROL AND STATUS REGISTER
;**********************************************************
; The USB Control and Status Register provides three 
; functions. It allows for direct read of the D+/D- bits,
; it contains a flag indicating USB bus activity, and it
; provides the means for controlling the D+/D- bits 
; directly. 
;
; D+/D- control can be used for two different applications. 
; Under normal operation, certain variations of the D+/D-
; bits are used to signal resume (remote wakeup) and USB
; reset. A variation can be implemented with the 4xx series
; of processors allowing the D+/D- pins to be connected to
; a PS/2 device rather than a USB device. In this mode,
; PS/2 support can be implemented via programmed I/O.
;**********************************************************

USB_CTL:            equ     1Fh             ; [R/W]

;.............. Fields ....................................

; If USB_CTL[7:6] = [1,1], 5 Endpoint FIFOs, 2 are 32 Bytes, 3 are 8 Bytes.
; If USB_CTL[7:6] = [1,0], 3 Endpoint FIFOs, 2 are 32 Bytes, 3 are 8 Bytes.
; If USB_CTL[7:6] = [0,1], 5 Endpoint FIFOs, All are 8 Bytes
; If USB_CTL[7:6] = [0,0], 3 Endpoint FIFOs, All are 8 Bytes.

EP_SIZE:            equ     80h             ; 8(0) or 32(1) byte FIFO
EP_COUNT:           equ     40h             ; 0 = 3 EPs; 1 = 5 EPs