n8bit.o

128X128的TFT并口驱动测试程序

XL
H 2 areas F global symbols
M n8bit.c
S push_gset2 Ref0000
S pop_gset2 Ref0000
A text size 306 flags 0
dbfile D:\taobao\src\n8bit.c
dbfunc e port_init 0 fV
dbline FFFFFFFF 0
dbline 32 0
dbline 33 0
dbline 34 4
dbline 35 8
dbline 36 C
dbline 37 E
dbline 38 10
dbline 39 12
dbline 3A 14
dbline FFFFFFFE 16
dbline 0 16
dbfunc e init_devices 18 fV
dbline FFFFFFFF 18
dbline 3F 18
dbline 40 18
dbline 41 1A
dbline 43 1C
dbline 44 20
dbline 45 22
dbline 46 24
dbline FFFFFFFE 26
dbline 0 26
dbfunc e Delay_1us 28 fV
dbline FFFFFFFF 28
dbline 4A 28
dbline 4B 28
dbline FFFFFFFE 2A
dbline 0 2A
dbfunc e Delay_nus 2C fV
dbsym r i 14 i
dbsym r n 16 i
dbline FFFFFFFF 32
dbline 4E 32
dbline 4F 32
dbline 50 36
dbline 51 38
dbline 50 3A
dbline 50 3E
dbline FFFFFFFE 44
dbline 0 48
dbfunc e Delay_1ms 4A fV
dbsym r i 10 i
dbline FFFFFFFF 4A
dbline 54 4A
dbline 56 4A
dbline 56 50
dbline 56 50
dbline 56 54
dbline FFFFFFFE 5C
dbline 0 5C
dbfunc e Delay_nms 5E fV
dbsym r i 14 i
dbsym r n 16 i
dbline FFFFFFFF 64
dbline 59 64
dbline 5A 64
dbline 5B 68
dbline 5C 6A
dbline 5B 6C
dbline 5B 70
dbline FFFFFFFE 76
dbline 0 7A
dbfunc e write_data 7C fV
dbsym r data 10 c
dbline FFFFFFFF 7C
dbline 60 7C
dbline 63 7C
dbline 63 7E
dbline 64 7E
dbline 64 80
dbline 66 80
dbline 67 82
dbline 67 84
dbline 69 84
dbline 69 86
dbline 6E 86
dbline 6E 88
dbline FFFFFFFE 88
dbline 0 88
dbfunc e write_data16 8A fV
dbsym r dataL 12 c
dbsym r dataH 10 c
dbline FFFFFFFF 8A
dbline 72 8A
dbline 75 8A
dbline 75 8C
dbline 76 8C
dbline 76 8E
dbline 77 8E
dbline 78 90
dbline 78 92
dbline 7A 92
dbline 7A 94
dbline 7B 94
dbline 7C 96
dbline 7C 98
dbline 7E 98
dbline 7E 9A
dbline 80 9A
dbline 80 9C
dbline FFFFFFFE 9C
dbline 0 9C
dbfunc e write_cmd 9E fV
dbsym r data 10 c
dbline FFFFFFFF 9E
dbline 83 9E
dbline 84 9E
dbline 84 A0
dbline 85 A0
dbline 85 A2
dbline 87 A2
dbline 88 A6
dbline 88 A8
dbline 8A A8
dbline 8A AA
dbline 8C AA
dbline 8D AC
dbline 8D AE
dbline 8F AE
dbline 8F B0
dbline 91 B0
dbline 91 B2
dbline FFFFFFFE B2
dbline 0 B2
dbfunc e LCD_WR_REG B4 fV
dbsym r dataL 14 c
dbsym r dataH 16 c
dbsym r data16 12 i
dbsym r reg 10 c
dbline FFFFFFFF B8
dbline 95 B8
dbline 97 B8
dbline 98 BE
dbline 99 C2
dbline 99 C4
dbline 9A C4
dbline 9A C6
dbline 9D C6
dbline 9E CA
dbline 9E CC
dbline A0 CC
dbline A0 CE
dbline A2 CE
dbline A3 D0
dbline A3 D2
dbline A5 D2
dbline A5 D4
dbline A6 D4
dbline A6 D6
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dbline A8 D8
dbline A8 DA
dbline AA DA
dbline AA DC
dbline AB DC
dbline AC DE
dbline AC E0
dbline AE E0
dbline AE E2
dbline B2 E2
dbline B2 E4
dbline FFFFFFFE E4
dbline 0 E8
dbfunc e LCD_Init EA fV
dbline FFFFFFFF EA
dbline B8 EA
dbline BA EA
dbline BB F2
dbline BC FA
dbline BD 102
dbline BE 10A
dbline BF 112
dbline C0 118
dbline C1 120
dbline C2 126
dbline C3 12E
dbline C4 136
dbline C5 13E
dbline C6 146
dbline C7 14E
dbline C8 156
dbline C9 15E
dbline CA 166
dbline CB 16E
dbline CC 176
dbline CD 17E
dbline CE 186
dbline CF 18E
dbline D0 196
dbline D1 19E
dbline D2 1A6
dbline D3 1AE
dbline D4 1B6
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dbline D6 1C6
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dbline D9 1DE
dbline DA 1E4
dbline DB 1EC
dbline DC 1F2
dbline DD 1FA
dbline E0 200
dbline E1 208
dbline E2 210
dbline E3 218
dbline E6 21C
dbline E7 224
dbline E8 22A
dbline E9 232
dbline EA 238
dbline EB 240
dbline EC 246
dbline ED 24E
dbline EE 254
dbline EF 25C
dbline F0 262
dbline FFFFFFFE 266
dbline 0 266
dbfunc e main 268 fV
dbsym l j 1 i
dbsym r i 14 i
dbline FFFFFFFF 268
dbline FA 268
dbline FC 268
dbline FD 26A
dbline FD 26C
dbline FF 26C
dbline 100 272
dbline 100 274
dbline 101 274
dbline 102 27A
dbline 102 27C
dbline 103 27C
dbline 104 282
dbline 105 284
dbline 106 28C
dbline 107 290
dbline 108 296
dbline 109 29A
dbline 10A 2A0
dbline 10D 2A4
dbline 10E 2AA
dbline 10D 2B0
dbline 10D 2B4
dbline 110 2BC
dbline 111 2C4
dbline 112 2C8
dbline 113 2CE
dbline 114 2D2
dbline 115 2D8
dbline 118 2DC
dbline 119 2E2
dbline 118 2F0
dbline 118 2F4
dbline 11C 2FC
dbline 11D 302
dbline 11D 304
dbline FFFFFFFE 304
dbline 0 304
S _Delay_nus Def002C
S _main Def0268
S _write_cmd Def009E
S _LCD_Init Def00EA
S _port_init Def0000
S _init_devices Def0018
S _LCD_WR_REG Def00B4
S _write_data Def007C
S _Delay_1ms Def004A
S _Delay_1us Def0028
S _write_data16 Def008A
S _Delay_nms Def005E
A lit size 48C0 flags 0
dbsym e AVR_LOGO 0 A[18624:18624]kc
S _AVR_LOGO Def0000
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R 00 00 00 00
T 0E 00 25 BA 24 BA 82 BB 81 BB 08 95
R 00 00 00 00
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R 00 00 00 00
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R 00 00 00 00
T 28 00 00 00 08 95
R 00 00 00 00
T 2C 00 0E 94 00 00 B8 01 44 27 55 27 03 C0 F7 DF
R 00 00 00 00 12 04 00 00
T 3A 00 4F 5F 5F 4F 46 17 57 07 D0 F3 0E 94 00 00
R 00 00 00 00 12 0E 01 00
T 48 00 08 95
R 00 00 00 00
T 4A 00 00 27 11 27 02 C0 0F 5F 1F 4F 04 37 E4 E0
R 00 00 00 00
T 58 00 1E 07 D0 F3 08 95
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R 00 00 00 00 12 0E 01 00
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T 02 03 DC 9A 08 95
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R 00 00 01 00
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R 00 00 01 00
T 54 00 BE 5F BE 5F BE 5F BE 5F BE 5F BE 5F BE 5F
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