📄 erjiguan_deng.tan.rpt
字号:
; N/A ; None ; 17.000 ns ; q[2] ; led[5] ; clk ;
; N/A ; None ; 17.000 ns ; q[1] ; led[5] ; clk ;
+-------+--------------+------------+------+--------+------------+
+-------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+--------+
; N/A ; None ; 15.000 ns ; c ; led[0] ;
; N/A ; None ; 15.000 ns ; c ; led[2] ;
; N/A ; None ; 15.000 ns ; c ; led[3] ;
; N/A ; None ; 15.000 ns ; c ; led[4] ;
; N/A ; None ; 15.000 ns ; c ; led[6] ;
; N/A ; None ; 15.000 ns ; c ; led[7] ;
; N/A ; None ; 15.000 ns ; c ; led[1] ;
; N/A ; None ; 15.000 ns ; c ; led[5] ;
+-------+-------------------+-----------------+------+--------+
+--------------------------------------------------------------------------------+
; Minimum tco ;
+---------------+------------------+----------------+------+--------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+------+--------+------------+
; N/A ; None ; 17.000 ns ; q[1] ; led[5] ; clk ;
; N/A ; None ; 17.000 ns ; q[2] ; led[5] ; clk ;
; N/A ; None ; 17.000 ns ; q[3] ; led[5] ; clk ;
; N/A ; None ; 17.000 ns ; q[0] ; led[5] ; clk ;
; N/A ; None ; 17.000 ns ; q[1] ; led[1] ; clk ;
; N/A ; None ; 17.000 ns ; q[2] ; led[1] ; clk ;
; N/A ; None ; 17.000 ns ; q[3] ; led[1] ; clk ;
; N/A ; None ; 17.000 ns ; q[0] ; led[1] ; clk ;
; N/A ; None ; 17.000 ns ; q[1] ; led[7] ; clk ;
; N/A ; None ; 17.000 ns ; q[2] ; led[7] ; clk ;
; N/A ; None ; 17.000 ns ; q[3] ; led[7] ; clk ;
; N/A ; None ; 17.000 ns ; q[0] ; led[7] ; clk ;
; N/A ; None ; 17.000 ns ; q[1] ; led[6] ; clk ;
; N/A ; None ; 17.000 ns ; q[2] ; led[6] ; clk ;
; N/A ; None ; 17.000 ns ; q[3] ; led[6] ; clk ;
; N/A ; None ; 17.000 ns ; q[0] ; led[6] ; clk ;
; N/A ; None ; 17.000 ns ; q[1] ; led[4] ; clk ;
; N/A ; None ; 17.000 ns ; q[2] ; led[4] ; clk ;
; N/A ; None ; 17.000 ns ; q[3] ; led[4] ; clk ;
; N/A ; None ; 17.000 ns ; q[0] ; led[4] ; clk ;
; N/A ; None ; 17.000 ns ; q[1] ; led[3] ; clk ;
; N/A ; None ; 17.000 ns ; q[2] ; led[3] ; clk ;
; N/A ; None ; 17.000 ns ; q[3] ; led[3] ; clk ;
; N/A ; None ; 17.000 ns ; q[0] ; led[3] ; clk ;
; N/A ; None ; 17.000 ns ; q[1] ; led[2] ; clk ;
; N/A ; None ; 17.000 ns ; q[2] ; led[2] ; clk ;
; N/A ; None ; 17.000 ns ; q[3] ; led[2] ; clk ;
; N/A ; None ; 17.000 ns ; q[0] ; led[2] ; clk ;
; N/A ; None ; 17.000 ns ; q[1] ; led[0] ; clk ;
; N/A ; None ; 17.000 ns ; q[2] ; led[0] ; clk ;
; N/A ; None ; 17.000 ns ; q[3] ; led[0] ; clk ;
; N/A ; None ; 17.000 ns ; q[0] ; led[0] ; clk ;
+---------------+------------------+----------------+------+--------+------------+
+---------------------------------------------------------------------+
; Minimum tpd ;
+---------------+-------------------+-----------------+------+--------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+------+--------+
; N/A ; None ; 15.000 ns ; c ; led[5] ;
; N/A ; None ; 15.000 ns ; c ; led[1] ;
; N/A ; None ; 15.000 ns ; c ; led[7] ;
; N/A ; None ; 15.000 ns ; c ; led[6] ;
; N/A ; None ; 15.000 ns ; c ; led[4] ;
; N/A ; None ; 15.000 ns ; c ; led[3] ;
; N/A ; None ; 15.000 ns ; c ; led[2] ;
; N/A ; None ; 15.000 ns ; c ; led[0] ;
+---------------+-------------------+-----------------+------+--------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Sat May 23 10:23:55 2009
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off erjiguan_deng -c erjiguan_deng
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 76.92 MHz between source register q[0] and destination register q[1] (period= 13.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC39; Fanout = 24; REG Node = 'q[0]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC36; Fanout = 26; REG Node = 'q[1]'
Info: Total cell delay = 6.000 ns ( 75.00 % )
Info: Total interconnect delay = 2.000 ns ( 25.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock clk to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 26; REG Node = 'q[1]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: - Longest clock path from clock clk to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC39; Fanout = 24; REG Node = 'q[0]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock clk to destination pin led[0] through register q[0] is 17.000 ns
Info: + Longest clock path from clock clk to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC39; Fanout = 24; REG Node = 'q[0]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 13.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC39; Fanout = 24; REG Node = 'q[0]'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC45; Fanout = 1; COMB Node = 'p2~769'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'led[0]'
Info: Total cell delay = 11.000 ns ( 84.62 % )
Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Longest tpd from source pin c to destination pin led[0] is 15.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_63; Fanout = 23; PIN Node = 'c'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC45; Fanout = 1; COMB Node = 'p2~769'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'led[0]'
Info: Total cell delay = 13.000 ns ( 86.67 % )
Info: Total interconnect delay = 2.000 ns ( 13.33 % )
Info: Minimum tco from clock clk to destination pin led[5] through register q[1] is 17.000 ns
Info: + Shortest clock path from clock clk to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 26; REG Node = 'q[1]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Shortest register to pin delay is 13.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 26; REG Node = 'q[1]'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC35; Fanout = 1; COMB Node = 'p2~739'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'led[5]'
Info: Total cell delay = 11.000 ns ( 84.62 % )
Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Shortest tpd from source pin c to destination pin led[5] is 15.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_63; Fanout = 23; PIN Node = 'c'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC35; Fanout = 1; COMB Node = 'p2~739'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'led[5]'
Info: Total cell delay = 13.000 ns ( 86.67 % )
Info: Total interconnect delay = 2.000 ns ( 13.33 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Sat May 23 10:23:56 2009
Info: Elapsed time: 00:00:00
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