erjiguan_deng.map.qmsg

8个发光二级管

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 23 10:23:43 2009 " "Info: Processing started: Sat May 23 10:23:43 2009" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off erjiguan_deng -c erjiguan_deng " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off erjiguan_deng -c erjiguan_deng" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "erjiguan_deng.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file erjiguan_deng.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 erjiguan_deng-a " "Info: Found design unit 1: erjiguan_deng-a" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "erjiguan_deng-a" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 erjiguan_deng " "Info: Found entity 1: erjiguan_deng" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "erjiguan_deng" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clr erjiguan_deng.vhd(22) " "Warning: VHDL Process Statement warning at erjiguan_deng.vhd(22): signal clr is in statement, but is not in sensitivity list" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "c erjiguan_deng.vhd(37) " "Warning: VHDL Process Statement warning at erjiguan_deng.vhd(37): signal c is in statement, but is not in sensitivity list" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 37 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q erjiguan_deng.vhd(38) " "Warning: VHDL Process Statement warning at erjiguan_deng.vhd(38): signal q is in statement, but is not in sensitivity list" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 38 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "c erjiguan_deng.vhd(51) " "Warning: VHDL Process Statement warning at erjiguan_deng.vhd(51): signal c is in statement, but is not in sensitivity list" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 51 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q erjiguan_deng.vhd(52) " "Warning: VHDL Process Statement warning at erjiguan_deng.vhd(52): signal q is in statement, but is not in sensitivity list" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 52 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "led erjiguan_deng.vhd(33) " "Warning: VHDL Process Statement warning at erjiguan_deng.vhd(33): signal or variable led may not be assigned a new value in every possible path through the Process Statement. Signal or variable led holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 33 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "led\[6\]\$latch " "Warning: LATCH primitive led\[6\]\$latch is permanently enabled" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "led\[5\]\$latch " "Warning: LATCH primitive led\[5\]\$latch is permanently enabled" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "led\[4\]\$latch " "Warning: LATCH primitive led\[4\]\$latch is permanently enabled" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "led\[3\]\$latch " "Warning: LATCH primitive led\[3\]\$latch is permanently enabled" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "led\[2\]\$latch " "Warning: LATCH primitive led\[2\]\$latch is permanently enabled" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "led\[1\]\$latch " "Warning: LATCH primitive led\[1\]\$latch is permanently enabled" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "led\[0\]\$latch " "Warning: LATCH primitive led\[0\]\$latch is permanently enabled" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "led\[7\]\$latch " "Warning: LATCH primitive led\[7\]\$latch is permanently enabled" {  } { { "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" "" "" { Text "D:/第三周  试验  07607邓习海/发光 二级管/erjiguan_deng.vhd" 33 -1 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin clk to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "23 " "Info: Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "12 " "Info: Implemented 12 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 23 10:23:47 2009 " "Info: Processing ended: Sat May 23 10:23:47 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}