erjiguan_deng.vhd

来自「8个发光二级管」· VHDL 代码 · 共 69 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity erjiguan_deng is
 port
     (clr,clk,c:in std_logic;
     led: out std_logic_vector(7 downto 0));
     
     end erjiguan_deng;
     

architecture a of erjiguan_deng is

signal q: std_logic_vector(3 downto 0);


begin 
p1: process(clk)

begin
if clr='0' then q<="0000";
elsif(clk'event and clk='1')then
if q="1000"then
   q<="0000";
   else q<=q+1;
   end if;
   end if;

   end process;
   
   
p2:process(clk)

begin

if(c='1')then
case q is

when "0000"=>led<="00000000";
when "0001"=>led<="00000001";
when "0010"=>led<="00000010";
when "0011"=>led<="00000100";
when "0100"=>led<="00001000";
when "0101"=>led<="00010000";
when "0110"=>led<="00100000";
when "0111"=>led<="01000000";
when "1000"=>led<="10000000";
when others=>led <="00000000";
end case;
elsif (c='0')then 
case q is 

when "0000"=>led<="00011000";
when "0001"=>led<="00111100";
when "0010"=>led<="01111110";
when "0011"=>led<="11111111";
when "0100"=>led<="01111110";
when "0101"=>led<="00111100";
when "0110"=>led<="00011000";
when "0111"=>led<="00000000";
when "1000"=>led<="00011000";
when others=>led <="00000000";
end case;
end if;

end process;

end a;