path.v

verilog实现卷积码的译码

/******************************************************/   
/*   module memory                                    */   
/******************************************************/   
// ---------------------------------------------------------------------------
// Purpose 	: Basic unit for the path_memory.
// --
// File name	: path.v
// Author	: M. Zalfany Urfianto
//		  <[e-mail]>
// Last Rev.	: 18.4.2001
// 
// Modules used : dff.v
// --
// Simulator	: ModelSim PE/Plus 4.7h
// Error	: None known yet.
// ---------------------------------------------------------------------------

module path(in,out,clk,reset);   

   input [3:0] in; 
   input clk,reset; 
   output [3:0] out;   
   
   wire [3:0] p_in;   
   
   dff #(4) path0(p_in,out,clk,reset);   

   assign p_in = in;

endmodule