hardware.lst
来自「利用凌阳61单片机实现输液的智能监控及语音报警」· LST 代码 · 共 1,052 行 · 第 1/4 页
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00008FB5 09 93 FF FF r1 = 0xffff
00008FB7 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
00008FB9 40 92 r1 =0x0000 //
// r1 = [R_InterruptStatus] //
00008FBA 11 93 2D 70 r1 = [P_INT_Mask]
00008FBC 09 A3 00 10 r1 |= C_IRQ1_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz
00008FBE 19 D3 18 03 [R_InterruptStatus] = r1 //
00008FC0 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008FC2 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
00008FC3 40 92 r1 = 0x0000 // 24MHz Fosc
00008FC4 19 D3 13 70 [P_SystemClock]=r1 // Initial System Clock
00008FC6 70 92 r1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008FC7 19 D3 0B 70 [P_TimerA_Ctrl]=r1 // Initial Timer A
//R1 = 0xfd00 // 16K
00008FC9 09 93 ED FC r1 = 0xfced // 15.625K
00008FCB 19 D3 0A 70 [P_TimerA_Data]=r1
00008FCD 09 93 A8 00 r1 = 0x00A8 //
00008FCF 19 D3 2A 70 [P_DAC_Ctrl] = r1 //
00008FD1 09 93 FF FF r1 = 0xffff
00008FD3 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
// R1 = [R_InterruptStatus] //
00008FD5 11 93 2D 70 r1 = [P_INT_Mask]
00008FD7 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
00008FD9 19 D3 18 03 [R_InterruptStatus] = r1 //
00008FDB 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008FDD 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
00008FDE 60 92 r1=0x0020;
00008FDF 19 D3 13 70 [P_SystemClock]=r1
00008FE1 09 93 A8 00 r1 = 0x00A8; //
00008FE3 19 D3 2A 70 [P_DAC_Ctrl]= r1
00008FE5 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008FE6 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
00008FE8 09 93 00 FE r1 = 0xfe00; // 24K
00008FEA 19 D3 0A 70 [P_TimerA_Data] = r1;
00008FEC 09 93 FF FF r1 = 0xffff
00008FEE 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
// r1 = [R_InterruptStatus] //
00008FF0 11 93 2D 70 r1 = [P_INT_Mask]
00008FF2 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
00008FF4 19 D3 18 03 [R_InterruptStatus] = r1 //
00008FF6 19 D3 10 70 [P_INT_Ctrl] = r1 //
00008FF8 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
00008FF9 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
00008FFA 19 D3 13 70 [P_SystemClock] = r1; // Initial System Clock
00008FFC 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00008FFD 19 D3 0B 70 [P_TimerA_Ctrl] = r1 // Initial Timer A
//R1 = 0x0003 // 8K
00008FFF 40 92 r1 = 0x0000 // Fosc/2
00009000 19 D3 0D 70 [P_TimerB_Ctrl] = r1; // Initial Timer B -> 8192
//R1 = 0xFFFF
00009002 09 93 00 FA r1 = 0xFA00 // Any time for ADPCM channel 0,1
00009004 19 D3 0C 70 [P_TimerB_Data] = r1 // 8K sample rate
00009006 09 93 FF FF r1 = 0xffff
00009008 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
0000900A 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
0000900B 46 92 r1 = 0x0006
0000900C 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000900E 09 93 00 FE r1 = 0xFE00
00009010 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
00009012 11 93 2D 70 r1 = [P_INT_Mask]
00009014 09 A3 10 84 r1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
00009016 19 D3 18 03 [R_InterruptStatus] = r1 //
00009018 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000901A 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
0000901B 09 93 A8 00 r1 = 0x00A8
0000901D 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000901F 09 93 00 FE r1 = 0xFE00
00009021 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
00009023 11 93 2D 70 r1 = [P_INT_Mask]
00009025 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00009027 19 D3 18 03 [R_InterruptStatus] = r1 //
00009029 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000902B 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
0000902C 09 93 A8 00 r1 = 0x00A8
0000902E 19 D3 2A 70 [P_DAC_Ctrl] = r1
00009030 09 93 9A FD r1 = 0xFD9A
00009032 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
00009034 11 93 2D 70 r1 = [P_INT_Mask]
00009036 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00009038 19 D3 18 03 [R_InterruptStatus] = r1 //
0000903A 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000903C 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
0000903D 09 93 A8 00 r1 = 0x00A8
0000903F 19 D3 2A 70 [P_DAC_Ctrl] = r1
00009041 09 93 00 FD r1 = 0xFD00
00009043 19 D3 0A 70 [P_TimerA_Data] = r1 //
// r1 = [R_InterruptStatus] //
00009045 11 93 2D 70 r1 = [P_INT_Mask]
// r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
00009047 19 D3 18 03 [R_InterruptStatus] = r1 //
00009049 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000904B 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
0000904C 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
0000904D 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
0000904F 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00009050 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
00009052 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
00009054 19 D3 0A 70 [P_TimerA_Data] = r1;
00009056 75 92 r1 = 0x0035; // ADINI should be open (107)
00009057 19 D3 15 70 [P_ADC_Ctrl] = r1;
00009059 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
0000905B 19 D3 2A 70 [P_DAC_Ctrl] = r1;
0000905D 09 93 FF FF r1 = 0xffff;
0000905F 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
// r1 = [R_InterruptStatus] //
00009061 11 93 2D 70 r1 = [P_INT_Mask]
00009063 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
00009065 19 D3 18 03 [R_InterruptStatus] = r1 //
00009067 19 D3 10 70 [P_INT_Ctrl] = r1 //
00009069 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
0000906A 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
0000906B 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
0000906D 09 93 00 FE r1=0xfe00; //24K @ 24.576MHz
0000906F 19 D3 0A 70 [P_TimerA_Data] = r1
00009071 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
00009072 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
00009073 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
00009075 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
00009077 19 D3 0A 70 [P_TimerA_Data] = r1;
00009079 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
0000907A 90 D4 push r1,r2 to [sp]
0000907B 11 93 17 70 r1=[P_DAC1]
0000907D 09 B3 C0 FF r1 &= ~0x003f
0000907F 09 43 00 80 cmp r1,0x8000
00009081 0E 0E jb L_RU_NormalUp
00009082 19 5E je L_RU_End
L_RU_DownLoop:
00009083 40 F0 E6 90 call F_Delay
00009085 41 94 r2 = 0x0001
00009086 1A D5 12 70 [P_Watchdog_Clear] = r2
00009088 09 23 40 00 r1 -= 0x40
0000908A 19 D3 17 70 [P_DAC1] = r1
0000908C 09 43 00 80 cmp r1,0x8000
0000908E 4C 4E jne L_RU_DownLoop
L_RD_DownEnd:
0000908F 0C EE jmp L_RU_End
L_RU_NormalUp:
L_RU_Loop:
00009090 40 F0 E6 90 call F_Delay
00009092 41 94 r2 = 0x0001
00009093 1A D5 12 70 [P_Watchdog_Clear] = r2
00009095 09 03 40 00 r1 += 0x40
00009097 19 D3 17 70 [P_DAC1] = r1
00009099 09 43 00 80 cmp r1, 0x8000
0000909B 4C 4E jne L_RU_Loop
L_RU_End:
0000909C 90 90 pop r1,r2 from [sp]
0000909D 90 9A retf
.ENDP
//............................................................
_SP_RampDnDAC1: .PROC
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