ccdcontrol.tan.qmsg

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

{ "Info" "ITDB_TH_RESULT" "iag~reg0 reset clk -2.159 ns register " "Info: th for register \"iag~reg0\" (data pin = \"reset\", clock pin = \"clk\") is -2.159 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 74 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns iag~reg0 2 REG LC_X5_Y3_N6 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N6; Fanout = 2; REG Node = 'iag~reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk iag~reg0 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk iag~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout iag~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.728 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns reset 1 PIN PIN_12 43 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 43; PIN Node = 'reset'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.489 ns) + CELL(0.740 ns) 4.392 ns srg~542 2 COMB LC_X5_Y3_N1 3 " "Info: 2: + IC(2.489 ns) + CELL(0.740 ns) = 4.392 ns; Loc. = LC_X5_Y3_N1; Fanout = 3; COMB Node = 'srg~542'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.229 ns" { reset srg~542 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.591 ns) 5.728 ns iag~reg0 3 REG LC_X5_Y3_N6 2 " "Info: 3: + IC(0.745 ns) + CELL(0.591 ns) = 5.728 ns; Loc. = LC_X5_Y3_N6; Fanout = 2; REG Node = 'iag~reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.336 ns" { srg~542 iag~reg0 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.494 ns ( 43.54 % ) " "Info: Total cell delay = 2.494 ns ( 43.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.234 ns ( 56.46 % ) " "Info: Total interconnect delay = 3.234 ns ( 56.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.728 ns" { reset srg~542 iag~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.728 ns" { reset reset~combout srg~542 iag~reg0 } { 0.000ns 0.000ns 2.489ns 0.745ns } { 0.000ns 1.163ns 0.740ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk iag~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout iag~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.728 ns" { reset srg~542 iag~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.728 ns" { reset reset~combout srg~542 iag~reg0 } { 0.000ns 0.000ns 2.489ns 0.745ns } { 0.000ns 1.163ns 0.740ns 0.591ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Allocated 126 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 11 21:47:17 2008 " "Info: Processing ended: Wed Jun 11 21:47:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}