ccdcontrol.tan.qmsg

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } } { "d:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "adreset " "Info: Assuming node \"adreset\" is an undefined clock" {  } { { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } } { "d:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "adreset" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register readcnt\[0\] register srgcyc\[6\] 59.95 MHz 16.681 ns Internal " "Info: Clock \"clk\" has Internal fmax of 59.95 MHz between source register \"readcnt\[0\]\" and destination register \"srgcyc\[6\]\" (period= 16.681 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.972 ns + Longest register register " "Info: + Longest register to register delay is 15.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns readcnt\[0\] 1 REG LC_X7_Y1_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N4; Fanout = 3; REG Node = 'readcnt\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { readcnt[0] } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.296 ns) + CELL(0.747 ns) 2.043 ns Add2~397 2 COMB LC_X6_Y1_N0 2 " "Info: 2: + IC(1.296 ns) + CELL(0.747 ns) = 2.043 ns; Loc. = LC_X6_Y1_N0; Fanout = 2; COMB Node = 'Add2~397'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { readcnt[0] Add2~397 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.166 ns Add2~395 3 COMB LC_X6_Y1_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.166 ns; Loc. = LC_X6_Y1_N1; Fanout = 2; COMB Node = 'Add2~395'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add2~397 Add2~395 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.289 ns Add2~393 4 COMB LC_X6_Y1_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.289 ns; Loc. = LC_X6_Y1_N2; Fanout = 2; COMB Node = 'Add2~393'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add2~395 Add2~393 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.412 ns Add2~389 5 COMB LC_X6_Y1_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.412 ns; Loc. = LC_X6_Y1_N3; Fanout = 2; COMB Node = 'Add2~389'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add2~393 Add2~389 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 2.673 ns Add2~391 6 COMB LC_X6_Y1_N4 5 " "Info: 6: + IC(0.000 ns) + CELL(0.261 ns) = 2.673 ns; Loc. = LC_X6_Y1_N4; Fanout = 5; COMB Node = 'Add2~391'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { Add2~389 Add2~391 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 3.648 ns Add2~400 7 COMB LC_X6_Y1_N8 6 " "Info: 7: + IC(0.000 ns) + CELL(0.975 ns) = 3.648 ns; Loc. = LC_X6_Y1_N8; Fanout = 6; COMB Node = 'Add2~400'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { Add2~391 Add2~400 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.262 ns) + CELL(0.740 ns) 5.650 ns readcnt\[0\]~1225 8 COMB LC_X5_Y1_N6 8 " "Info: 8: + IC(1.262 ns) + CELL(0.740 ns) = 5.650 ns; Loc. = LC_X5_Y1_N6; Fanout = 8; COMB Node = 'readcnt\[0\]~1225'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.002 ns" { Add2~400 readcnt[0]~1225 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.054 ns) + CELL(0.511 ns) 8.215 ns LessThan6~190 9 COMB LC_X6_Y2_N5 3 " "Info: 9: + IC(2.054 ns) + CELL(0.511 ns) = 8.215 ns; Loc. = LC_X6_Y2_N5; Fanout = 3; COMB Node = 'LessThan6~190'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.565 ns" { readcnt[0]~1225 LessThan6~190 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1583 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.960 ns) + CELL(0.200 ns) 10.375 ns srgcyc~515 10 COMB LC_X6_Y2_N1 5 " "Info: 10: + IC(1.960 ns) + CELL(0.200 ns) = 10.375 ns; Loc. = LC_X6_Y2_N1; Fanout = 5; COMB Node = 'srgcyc~515'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.160 ns" { LessThan6~190 srgcyc~515 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.714 ns) + CELL(0.200 ns) 11.289 ns srgcyc~516 11 COMB LC_X6_Y2_N8 4 " "Info: 11: + IC(0.714 ns) + CELL(0.200 ns) = 11.289 ns; Loc. = LC_X6_Y2_N8; Fanout = 4; COMB Node = 'srgcyc~516'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.914 ns" { srgcyc~515 srgcyc~516 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.200 ns) 12.213 ns srgcyc~517 12 COMB LC_X6_Y2_N0 4 " "Info: 12: + IC(0.724 ns) + CELL(0.200 ns) = 12.213 ns; Loc. = LC_X6_Y2_N0; Fanout = 4; COMB Node = 'srgcyc~517'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.924 ns" { srgcyc~516 srgcyc~517 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.200 ns) 14.213 ns srgcyc~527 13 COMB LC_X6_Y3_N0 2 " "Info: 13: + IC(1.800 ns) + CELL(0.200 ns) = 14.213 ns; Loc. = LC_X6_Y3_N0; Fanout = 2; COMB Node = 'srgcyc~527'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { srgcyc~517 srgcyc~527 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.168 ns) + CELL(0.591 ns) 15.972 ns srgcyc\[6\] 14 REG LC_X6_Y3_N6 3 " "Info: 14: + IC(1.168 ns) + CELL(0.591 ns) = 15.972 ns; Loc. = LC_X6_Y3_N6; Fanout = 3; REG Node = 'srgcyc\[6\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.759 ns" { srgcyc~527 srgcyc[6] } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.994 ns ( 31.27 % ) " "Info: Total cell delay = 4.994 ns ( 31.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.978 ns ( 68.73 % ) " "Info: Total interconnect delay = 10.978 ns ( 68.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.972 ns" { readcnt[0] Add2~397 Add2~395 Add2~393 Add2~389 Add2~391 Add2~400 readcnt[0]~1225 LessThan6~190 srgcyc~515 srgcyc~516 srgcyc~517 srgcyc~527 srgcyc[6] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "15.972 ns" { readcnt[0] Add2~397 Add2~395 Add2~393 Add2~389 Add2~391 Add2~400 readcnt[0]~1225 LessThan6~190 srgcyc~515 srgcyc~516 srgcyc~517 srgcyc~527 srgcyc[6] } { 0.000ns 1.296ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.262ns 2.054ns 1.960ns 0.714ns 0.724ns 1.800ns 1.168ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.123ns 0.261ns 0.975ns 0.740ns 0.511ns 0.200ns 0.200ns 0.200ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 74 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns srgcyc\[6\] 2 REG LC_X6_Y3_N6 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y3_N6; Fanout = 3; REG Node = 'srgcyc\[6\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk srgcyc[6] } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk srgcyc[6] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout srgcyc[6] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 74 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns readcnt\[0\] 2 REG LC_X7_Y1_N4 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y1_N4; Fanout = 3; REG Node = 'readcnt\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk readcnt[0] } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk readcnt[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout readcnt[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk srgcyc[6] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout srgcyc[6] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk readcnt[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout readcnt[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.972 ns" { readcnt[0] Add2~397 Add2~395 Add2~393 Add2~389 Add2~391 Add2~400 readcnt[0]~1225 LessThan6~190 srgcyc~515 srgcyc~516 srgcyc~517 srgcyc~527 srgcyc[6] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "15.972 ns" { readcnt[0] Add2~397 Add2~395 Add2~393 Add2~389 Add2~391 Add2~400 readcnt[0]~1225 LessThan6~190 srgcyc~515 srgcyc~516 srgcyc~517 srgcyc~527 srgcyc[6] } { 0.000ns 1.296ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.262ns 2.054ns 1.960ns 0.714ns 0.724ns 1.800ns 1.168ns } { 0.000ns 0.747ns 0.123ns 0.123ns 0.123ns 0.261ns 0.975ns 0.740ns 0.511ns 0.200ns 0.200ns 0.200ns 0.200ns 0.591ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk srgcyc[6] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout srgcyc[6] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk readcnt[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout readcnt[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "adreset " "Info: No valid register-to-register data paths exist for clock \"adreset\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "srg~reg0 reset clk 3.750 ns register " "Info: tsu for register \"srg~reg0\" (data pin = \"reset\", clock pin = \"clk\") is 3.750 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.765 ns + Longest pin register " "Info: + Longest pin to register delay is 6.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns reset 1 PIN PIN_12 43 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 43; PIN Node = 'reset'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.489 ns) + CELL(0.740 ns) 4.392 ns srg~542 2 COMB LC_X5_Y3_N1 3 " "Info: 2: + IC(2.489 ns) + CELL(0.740 ns) = 4.392 ns; Loc. = LC_X5_Y3_N1; Fanout = 3; COMB Node = 'srg~542'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.229 ns" { reset srg~542 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.737 ns) + CELL(0.740 ns) 5.869 ns srg~548 3 COMB LC_X5_Y3_N3 1 " "Info: 3: + IC(0.737 ns) + CELL(0.740 ns) = 5.869 ns; Loc. = LC_X5_Y3_N3; Fanout = 1; COMB Node = 'srg~548'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { srg~542 srg~548 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 6.765 ns srg~reg0 4 REG LC_X5_Y3_N4 3 " "Info: 4: + IC(0.305 ns) + CELL(0.591 ns) = 6.765 ns; Loc. = LC_X5_Y3_N4; Fanout = 3; REG Node = 'srg~reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.896 ns" { srg~548 srg~reg0 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.234 ns ( 47.80 % ) " "Info: Total cell delay = 3.234 ns ( 47.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.531 ns ( 52.20 % ) " "Info: Total interconnect delay = 3.531 ns ( 52.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.765 ns" { reset srg~542 srg~548 srg~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "6.765 ns" { reset reset~combout srg~542 srg~548 srg~reg0 } { 0.000ns 0.000ns 2.489ns 0.737ns 0.305ns } { 0.000ns 1.163ns 0.740ns 0.740ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 74 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns srg~reg0 2 REG LC_X5_Y3_N4 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N4; Fanout = 3; REG Node = 'srg~reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk srg~reg0 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk srg~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout srg~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.765 ns" { reset srg~542 srg~548 srg~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "6.765 ns" { reset reset~combout srg~542 srg~548 srg~reg0 } { 0.000ns 0.000ns 2.489ns 0.737ns 0.305ns } { 0.000ns 1.163ns 0.740ns 0.740ns 0.591ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk srg~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout srg~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk abg\[0\] abg\[0\]~reg0 8.130 ns register " "Info: tco from clock \"clk\" to destination pin \"abg\[0\]\" through register \"abg\[0\]~reg0\" is 8.130 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 74 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns abg\[0\]~reg0 2 REG LC_X5_Y3_N5 1 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N5; Fanout = 1; REG Node = 'abg\[0\]~reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk abg[0]~reg0 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk abg[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout abg[0]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.406 ns + Longest register pin " "Info: + Longest register to pin delay is 4.406 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns abg\[0\]~reg0 1 REG LC_X5_Y3_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N5; Fanout = 1; REG Node = 'abg\[0\]~reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { abg[0]~reg0 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.084 ns) + CELL(2.322 ns) 4.406 ns abg\[0\] 2 PIN PIN_85 0 " "Info: 2: + IC(2.084 ns) + CELL(2.322 ns) = 4.406 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'abg\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.406 ns" { abg[0]~reg0 abg[0] } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 52.70 % ) " "Info: Total cell delay = 2.322 ns ( 52.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.084 ns ( 47.30 % ) " "Info: Total interconnect delay = 2.084 ns ( 47.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.406 ns" { abg[0]~reg0 abg[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.406 ns" { abg[0]~reg0 abg[0] } { 0.000ns 2.084ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk abg[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout abg[0]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.406 ns" { abg[0]~reg0 abg[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.406 ns" { abg[0]~reg0 abg[0] } { 0.000ns 2.084ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}