prev_cmp_ccdcontrol.fit.qmsg

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "6 unused 3.30 1 5 0 " "Info: Number of I/O pins in group: 6 (unused VREF, 3.30 VCCIO, 1 input, 5 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 36 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "15.863 ns register register " "Info: Estimated most critical path is register to register delay of 15.863 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns readcnt\[0\] 1 REG LAB_X7_Y1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y1; Fanout = 3; REG Node = 'readcnt\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { readcnt[0] } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.351 ns) + CELL(0.978 ns) 2.329 ns Add2~397 2 COMB LAB_X6_Y1 2 " "Info: 2: + IC(1.351 ns) + CELL(0.978 ns) = 2.329 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'Add2~397'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.329 ns" { readcnt[0] Add2~397 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.452 ns Add2~395 3 COMB LAB_X6_Y1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.452 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'Add2~395'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add2~397 Add2~395 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.575 ns Add2~393 4 COMB LAB_X6_Y1 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.575 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'Add2~393'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add2~395 Add2~393 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.698 ns Add2~389 5 COMB LAB_X6_Y1 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.698 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'Add2~389'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add2~393 Add2~389 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 3.513 ns Add2~390 6 COMB LAB_X6_Y1 7 " "Info: 6: + IC(0.000 ns) + CELL(0.815 ns) = 3.513 ns; Loc. = LAB_X6_Y1; Fanout = 7; COMB Node = 'Add2~390'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { Add2~389 Add2~390 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.914 ns) 5.094 ns LessThan7~192 7 COMB LAB_X5_Y1 1 " "Info: 7: + IC(0.667 ns) + CELL(0.914 ns) = 5.094 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'LessThan7~192'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { Add2~390 LessThan7~192 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1583 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 6.274 ns LessThan7~193 8 COMB LAB_X5_Y1 2 " "Info: 8: + IC(0.980 ns) + CELL(0.200 ns) = 6.274 ns; Loc. = LAB_X5_Y1; Fanout = 2; COMB Node = 'LessThan7~193'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan7~192 LessThan7~193 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1583 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 7.454 ns LessThan7~194 9 COMB LAB_X5_Y1 2 " "Info: 9: + IC(0.980 ns) + CELL(0.200 ns) = 7.454 ns; Loc. = LAB_X5_Y1; Fanout = 2; COMB Node = 'LessThan7~194'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan7~193 LessThan7~194 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1583 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.914 ns) 9.728 ns srgcyc~515 10 COMB LAB_X6_Y2 5 " "Info: 10: + IC(1.360 ns) + CELL(0.914 ns) = 9.728 ns; Loc. = LAB_X6_Y2; Fanout = 5; COMB Node = 'srgcyc~515'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.274 ns" { LessThan7~194 srgcyc~515 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.511 ns) 10.908 ns srgcyc~516 11 COMB LAB_X6_Y2 4 " "Info: 11: + IC(0.669 ns) + CELL(0.511 ns) = 10.908 ns; Loc. = LAB_X6_Y2; Fanout = 4; COMB Node = 'srgcyc~516'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { srgcyc~515 srgcyc~516 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 12.088 ns srgcyc~517 12 COMB LAB_X6_Y2 4 " "Info: 12: + IC(0.980 ns) + CELL(0.200 ns) = 12.088 ns; Loc. = LAB_X6_Y2; Fanout = 4; COMB Node = 'srgcyc~517'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { srgcyc~516 srgcyc~517 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.074 ns) + CELL(0.200 ns) 14.362 ns srgcyc~527 13 COMB LAB_X6_Y3 2 " "Info: 13: + IC(2.074 ns) + CELL(0.200 ns) = 14.362 ns; Loc. = LAB_X6_Y3; Fanout = 2; COMB Node = 'srgcyc~527'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.274 ns" { srgcyc~517 srgcyc~527 } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(1.061 ns) 15.863 ns srgcyc\[7\] 14 REG LAB_X6_Y3 2 " "Info: 14: + IC(0.440 ns) + CELL(1.061 ns) = 15.863 ns; Loc. = LAB_X6_Y3; Fanout = 2; REG Node = 'srgcyc\[7\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { srgcyc~527 srgcyc[7] } "NODE_NAME" } } { "ccdcontrol.vhd" "" { Text "E:/ccdproject/ccdcontrol.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.362 ns ( 40.11 % ) " "Info: Total cell delay = 6.362 ns ( 40.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.501 ns ( 59.89 % ) " "Info: Total interconnect delay = 9.501 ns ( 59.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.863 ns" { readcnt[0] Add2~397 Add2~395 Add2~393 Add2~389 Add2~390 LessThan7~192 LessThan7~193 LessThan7~194 srgcyc~515 srgcyc~516 srgcyc~517 srgcyc~527 srgcyc[7] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "8 8 " "Info: Average interconnect usage is 8% of the available device resources. Peak interconnect usage is 8%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y5 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/ccdproject/ccdcontrol.fit.smsg " "Info: Generated suppressed messages file E:/ccdproject/ccdcontrol.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "187 " "Info: Allocated 187 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 11 21:39:14 2008 " "Info: Processing ended: Wed Jun 11 21:39:14 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}