ccdcontrol.vhd.bak

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ccdcontrol is
  port(clk,adreset,reset:in std_logic;abg:out std_logic_vector(1 downto 0);srg,iag,adclk: out std_logic);
end ccdcontrol;

architecture ccd of ccdcontrol is

signal   aden:std_logic:='0';

begin
   process(clk,reset)  --clc 40Mhz
   variable bloom   :std_logic_vector(9  downto 0);
   variable cnt     :std_logic_vector(4  downto 0);
   variable readcnt :std_logic_vector(11  downto 0);
   variable srgcyc  :std_logic_vector(9  downto 0);
   variable iagcyc  :std_logic_vector(9  downto 0);
   variable ccden   :std_logic;
   begin
    if(reset='1')then
      ccden:='1';
      bloom:="0000000000";
      cnt:="00000";
      readcnt:="000000000000";
      srgcyc:="0000000000";
      iagcyc:="0000000000";
    else
    if(clk'EVENT and clk='1' )then
    if(ccden='1')then
    if(bloom<50)then
    if(cnt=9) then 
      cnt:="00000";
      bloom:=bloom+1;
    else cnt:=cnt+1;
    
     if cnt<=5 then
          srg <='0';
          abg(0) <='1';
          abg(1) <='0';
     else  
          srg<='1';
          abg(0)<='0';
          abg(1)<='1';
     end if;
    end if; 
    
    else 
     if(iagcyc<=189)then
     readcnt:=readcnt+1;
     abg<="00";
     if(readcnt<=9)then
        iag<='0';
       srg<='0';
     elsif (readcnt<=43)then
        iag<='1';
        srg<='0';
     elsif (readcnt<=49)then
       iag<='1';
       srg<='1';
     elsif (readcnt<=83) then
       iag<='0';
       srg<='1';
     elsif (readcnt<=90) then
       iag<='0';
       srg<='0';
     else iag<='0';
        if(srgcyc<=216)then
          if(cnt=3)then   
             cnt:="00000" ;
             srgcyc:=srgcyc+1;
          else cnt:=cnt+1;
          end if;
          
          if(cnt<=1) then srg<='0';
          else srg<='1';
          end if;
        else iagcyc:=iagcyc+1;
             readcnt:="000000000000";
             srgcyc :="0000000000";

        end if;
                         
     end if; 
     end if;
    end if;
    end if;
    end if;
    end if;              
   end process;

   process(adreset,clk)
   begin
   if(adreset'event and adreset='1' )then
   aden<='1';
   end if;
   end process;

   process(clk,adreset,aden)
   variable iagad  :std_logic_vector(7 downto 0);
   variable srgad  :std_logic_vector(7 downto 0);
   variable count  :std_logic_vector(3 downto 0);
   variable  idal   :std_logic_vector(7 downto 0); 
   begin
   
   if(clk='1' and clk'event)then
   if(aden/='1' )then
     adclk<='1';
   else
   if(iagad<=189)then
   if(srgad<=216)then
     if(count=3)then
       count:="0000";
       srgad:=srgad+1;
     else count:=count+1;
       if(count<=2)then adclk<='0';
       else adclk<='1';
       end if;
     end if;
   else idal:=idal+1;
        if(idal=91)then
          idal:="00000000";
          srgad:="00000000";
          iagad:=iagad+1;
        end if;
   end if;
   end if;
   end if;
   end if;
   end process;
           

  
end ccd;