ccdcontrol.fit.rpt

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:20         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:20         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:5;1:15     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:4;1:8;2:8  ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:3;1:11;2:6 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:20         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:3;1:17     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:20         ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2;1:18     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:20         ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:20         ;
; LEs in Chains - Fit Attempt 1                                                  ; 42           ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0            ;
; LABs with Chains - Fit Attempt 1                                               ; 5            ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0            ;
; Time - Fit Attempt 1                                                           ; 1            ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.032        ;
+--------------------------------------------------------------------------------+--------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 8      ;
; Early Slack - Fit Attempt 1         ; -18315 ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 13     ;
; Mid Slack - Fit Attempt 1           ; -16821 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Late Wire Use - Fit Attempt 1       ; 14     ;
; Late Slack - Fit Attempt 1          ; -16821 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.031  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -12472 ;
; Early Wire Use - Fit Attempt 1      ; 10     ;
; Peak Regional Wire - Fit Attempt 1  ; 9      ;
; Mid Slack - Fit Attempt 1           ; -16528 ;
; Late Slack - Fit Attempt 1          ; -16528 ;
; Late Wire Use - Fit Attempt 1       ; 16     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.110  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Jun 11 21:47:00 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ccdcontrol -c ccdcontrol
Info: Selected device EPM240T100C5 for design "ccdcontrol"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Warning: No exact pin location assignment(s) for 8 pins of 8 total pins
    Info: Pin abg[0] not assigned to an exact location on the device
    Info: Pin abg[1] not assigned to an exact location on the device
    Info: Pin srg not assigned to an exact location on the device
    Info: Pin iag not assigned to an exact location on the device
    Info: Pin adclk not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin reset not assigned to an exact location on the device
    Info: Pin adreset not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted some destinations of signal "reset" to use Global clock in PIN 12
    Info: Destination "abg[0]~500" may be non-global or may not use global clock
    Info: Destination "srg~542" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 6 (unused VREF, 3.30 VCCIO, 1 input, 5 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 15.863 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y1; Fanout = 3; REG Node = 'readcnt[0]'
    Info: 2: + IC(1.351 ns) + CELL(0.978 ns) = 2.329 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'Add2~397'
    Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.452 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'Add2~395'
    Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.575 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'Add2~393'
    Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.698 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'Add2~389'
    Info: 6: + IC(0.000 ns) + CELL(0.815 ns) = 3.513 ns; Loc. = LAB_X6_Y1; Fanout = 7; COMB Node = 'Add2~390'
    Info: 7: + IC(0.667 ns) + CELL(0.914 ns) = 5.094 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'LessThan7~192'
    Info: 8: + IC(0.980 ns) + CELL(0.200 ns) = 6.274 ns; Loc. = LAB_X5_Y1; Fanout = 2; COMB Node = 'LessThan7~193'
    Info: 9: + IC(0.980 ns) + CELL(0.200 ns) = 7.454 ns; Loc. = LAB_X5_Y1; Fanout = 2; COMB Node = 'LessThan7~194'
    Info: 10: + IC(1.360 ns) + CELL(0.914 ns) = 9.728 ns; Loc. = LAB_X6_Y2; Fanout = 5; COMB Node = 'srgcyc~515'
    Info: 11: + IC(0.669 ns) + CELL(0.511 ns) = 10.908 ns; Loc. = LAB_X6_Y2; Fanout = 4; COMB Node = 'srgcyc~516'
    Info: 12: + IC(0.980 ns) + CELL(0.200 ns) = 12.088 ns; Loc. = LAB_X6_Y2; Fanout = 4; COMB Node = 'srgcyc~517'
    Info: 13: + IC(2.074 ns) + CELL(0.200 ns) = 14.362 ns; Loc. = LAB_X6_Y3; Fanout = 2; COMB Node = 'srgcyc~527'
    Info: 14: + IC(0.440 ns) + CELL(1.061 ns) = 15.863 ns; Loc. = LAB_X6_Y3; Fanout = 2; REG Node = 'srgcyc[7]'
    Info: Total cell delay = 6.362 ns ( 40.11 % )
    Info: Total interconnect delay = 9.501 ns ( 59.89 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 8% of the available device resources. Peak interconnect usage is 8%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file E:/ccdproject/ccdcontrol.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 187 megabytes of memory during processing
    Info: Processing ended: Wed Jun 11 21:47:06 2008
    Info: Elapsed time: 00:00:06


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/ccdproject/ccdcontrol.fit.smsg.