📄 ccdcontrol.rpt
字号:
- 2 - C 01 OR2 s ! 0 2 0 5 ~297~1
- 1 - C 06 AND2 0 4 0 7 :297
- 3 - C 06 OR2 s 0 4 0 3 ~321~1
- 2 - C 08 OR2 0 4 0 1 :428
- 1 - D 08 OR2 0 4 0 6 :574
- 3 - D 08 OR2 0 4 0 1 :589
- 1 - D 01 AND2 s 0 3 0 1 ~591~1
- 6 - F 13 OR2 s 0 4 0 2 ~679~1
- 8 - F 16 OR2 ! 0 3 0 2 :724
- 5 - F 01 AND2 s 0 2 0 5 ~737~1
- 3 - F 13 OR2 ! 0 4 0 2 :764
- 5 - F 13 OR2 ! 0 4 0 2 :822
- 7 - F 01 OR2 ! 0 3 0 5 :853
- 6 - F 01 OR2 ! 0 4 0 2 :883
- 5 - F 09 OR2 s 0 4 0 1 ~911~1
- 2 - F 18 OR2 s ! 0 4 0 3 ~911~2
- 2 - F 01 OR2 0 4 0 5 :911
- 4 - F 01 OR2 0 4 0 1 :943
- 3 - F 01 AND2 0 2 0 1 :958
- 1 - F 17 AND2 ! 0 3 0 13 :1028
- 1 - C 35 OR2 ! 0 4 0 1 :1035
- 1 - C 21 OR2 ! 0 3 0 1 :1050
- 2 - C 29 AND2 ! 0 3 0 1 :1063
- 1 - C 09 OR2 ! 0 3 0 10 :1093
- 8 - C 13 OR2 0 4 0 2 :1127
- 5 - C 13 OR2 0 4 0 2 :1133
- 2 - C 13 OR2 0 4 0 2 :1139
- 4 - C 06 OR2 0 3 0 2 :1145
- 6 - C 13 OR2 0 4 0 1 :1212
- 8 - F 13 OR2 0 3 0 4 :1526
- 2 - C 14 OR2 0 4 0 1 :1543
- 7 - F 13 OR2 s 0 3 0 1 ~1544~1
- 5 - C 14 AND2 s 0 2 0 9 ~1702~1
- 7 - C 14 OR2 s 0 2 0 3 ~2204~1
- 1 - F 13 OR2 s 0 3 0 3 ~2245~1
- 3 - C 14 OR2 0 4 0 1 :2250
- 4 - F 13 OR2 s 0 4 0 1 ~2251~1
- 4 - F 17 AND2 s 0 2 0 5 ~2407~1
- 8 - F 17 OR2 0 3 0 1 :2425
- 6 - C 14 OR2 0 3 0 1 :2494
- 5 - C 08 OR2 s 0 4 0 2 ~2822~1
- 1 - C 01 OR2 s 0 4 0 1 ~2828~1
- 5 - C 01 OR2 s 0 4 0 1 ~2828~2
- 7 - C 09 OR2 s 0 4 0 1 ~2834~1
- 8 - C 09 OR2 s 0 4 0 1 ~2834~2
- 3 - C 01 OR2 s 0 3 0 5 ~2840~1
- 3 - C 13 OR2 s 0 4 0 1 ~2840~2
- 4 - C 13 OR2 s 0 4 0 1 ~2840~3
- 5 - C 06 OR2 s 0 4 0 1 ~2846~1
- 6 - C 06 OR2 s 0 4 0 1 ~2846~2
- 7 - C 04 AND2 s ! 0 3 0 1 ~2888~1
- 2 - C 09 AND2 s ! 0 2 0 5 ~2912~1
- 8 - F 01 OR2 s 0 4 0 2 ~2924~1
- 7 - C 01 OR2 s 0 4 0 15 ~2930~1
- 7 - C 35 OR2 s 0 4 0 1 ~2930~2
- 4 - C 35 OR2 s 0 4 0 1 ~2936~1
- 6 - C 35 OR2 s 0 3 0 1 ~2936~2
- 2 - C 21 OR2 s 0 4 0 1 ~2942~1
- 5 - C 21 OR2 s 0 4 0 1 ~2948~1
- 7 - C 21 OR2 s 0 4 0 1 ~2954~1
- 4 - C 29 OR2 s 0 4 0 1 ~2960~1
- 6 - C 29 OR2 s 0 4 0 1 ~2966~1
- 1 - F 01 OR2 s 0 2 0 5 ~2972~1
- 4 - D 08 AND2 s ! 0 4 0 2 ~2996~1
- 2 - F 13 OR2 s 0 3 0 3 ~3032~1
- 7 - F 09 OR2 s 0 4 0 1 ~3068~1
- 2 - F 03 AND2 s 0 3 0 2 ~3068~2
- 5 - F 17 AND2 s 0 2 0 3 ~3074~1
- 7 - F 03 OR2 s 0 4 0 2 ~3074~2
- 3 - F 17 AND2 s ! 0 2 0 16 ~3092~1
- 2 - F 15 OR2 s 0 2 0 4 ~3092~2
- 5 - C 09 AND2 s 0 2 0 4 ~3205~1
- 8 - F 03 AND2 s 0 4 0 1 ~3205~2
- 4 - C 08 AND2 s 0 4 0 1 ~3205~3
- 6 - C 08 OR2 s 0 4 0 1 ~3205~4
- 2 - F 08 OR2 1 0 0 17 :3205
- 8 - F 25 DFFE + 0 3 0 3 count3 (:3278)
- 6 - F 25 DFFE + 0 3 0 4 count2 (:3279)
- 5 - F 36 DFFE + 0 3 0 3 count1 (:3280)
- 2 - F 25 DFFE + 0 1 0 4 count0 (:3281)
- 8 - F 20 DFFE + 0 3 0 2 srgad7 (:3282)
- 4 - F 30 DFFE + 0 4 0 4 srgad6 (:3283)
- 6 - F 31 DFFE + 0 3 0 3 srgad5 (:3284)
- 5 - F 31 DFFE + 0 3 0 5 srgad4 (:3285)
- 2 - F 20 DFFE + 0 3 0 2 srgad3 (:3286)
- 7 - F 26 DFFE + 0 3 0 3 srgad2 (:3287)
- 3 - F 26 DFFE + 0 3 0 5 srgad1 (:3288)
- 2 - F 30 DFFE + 0 3 0 7 srgad0 (:3289)
- 8 - B 20 DFFE + 0 3 0 2 idal7 (:3290)
- 5 - B 20 DFFE + 0 3 0 2 idal6 (:3291)
- 5 - B 34 DFFE + 0 3 0 3 idal5 (:3292)
- 1 - B 34 DFFE + 0 3 0 3 idal4 (:3293)
- 2 - B 34 DFFE + 0 3 0 2 idal3 (:3294)
- 1 - B 27 DFFE + 0 3 0 2 idal2 (:3295)
- 4 - B 27 DFFE + 0 3 0 2 idal1 (:3296)
- 7 - B 27 DFFE + 0 3 0 7 idal0 (:3297)
- 7 - F 36 DFFE + 0 3 0 2 iagad7 (:3298)
- 4 - F 36 DFFE + 0 3 0 2 iagad6 (:3299)
- 8 - F 22 DFFE + 0 3 0 2 iagad5 (:3300)
- 4 - F 22 DFFE + 0 3 0 3 iagad4 (:3301)
- 1 - F 22 DFFE + 0 2 0 4 iagad3 (:3302)
- 1 - F 35 DFFE + 0 3 0 2 iagad2 (:3303)
- 8 - F 35 DFFE + 0 2 0 3 iagad1 (:3304)
- 2 - F 35 DFFE + 0 1 0 3 iagad0 (:3305)
- 2 - B 27 AND2 s 0 2 0 7 ~3374~1
- 5 - F 30 AND2 s 0 2 0 5 ~3374~2
- 4 - F 31 AND2 s 0 2 0 5 ~3374~3
- 4 - F 26 AND2 s 0 3 0 1 ~3374~4
- 2 - F 31 AND2 s 0 4 0 1 ~3374~5
- 8 - F 30 AND2 s 0 3 0 1 ~3374~6
- 5 - F 25 OR2 s 0 4 0 1 ~3374~7
- 7 - F 25 OR2 s 0 4 0 1 ~3374~8
- 8 - F 36 AND2 s 0 4 0 1 ~3374~9
- 2 - F 36 OR2 0 4 0 8 :3374
- 2 - F 22 AND2 s ! 0 4 0 1 ~3379~1
- 6 - F 36 OR2 s ! 0 2 0 1 ~3441~1
- 1 - F 20 OR2 0 4 0 22 :3441
- 3 - F 20 AND2 0 3 0 1 :3451
- 8 - F 26 OR2 0 3 0 1 :3464
- 1 - F 25 OR2 ! 0 3 0 11 :3490
- 6 - F 20 OR2 0 4 0 1 :3584
- 2 - B 20 OR2 s 0 4 0 1 ~3664~1
- 1 - B 20 OR2 s 0 4 0 4 ~3664~2
- 7 - F 20 OR2 0 4 0 1 :3871
- 4 - F 20 OR2 0 3 0 10 :3879
- 7 - B 20 OR2 0 4 0 1 :3919
- 4 - F 25 OR2 s 0 4 0 1 ~4203~1
- 3 - F 28 OR2 s 0 3 0 1 ~4203~2
- 6 - F 30 OR2 s 0 3 0 1 ~4221~1
- 1 - F 30 AND2 s ! 0 2 0 6 ~4227~1
- 7 - F 31 AND2 s ! 0 4 0 2 ~4239~1
- 7 - F 30 OR2 s 0 4 0 1 ~4239~2
- 3 - F 30 OR2 s 0 2 0 6 ~4245~1
- 8 - F 31 OR2 s 0 4 0 1 ~4245~2
- 1 - F 31 OR2 s 0 4 0 1 ~4251~1
- 5 - F 20 OR2 s 0 4 0 1 ~4257~1
- 5 - F 26 OR2 s 0 4 0 1 ~4263~1
- 2 - F 26 OR2 s 0 4 0 1 ~4269~1
- 4 - B 20 OR2 s 0 4 0 1 ~4287~1
- 7 - B 34 OR2 s 0 4 0 1 ~4293~1
- 4 - B 34 OR2 s 0 4 0 1 ~4299~1
- 3 - B 34 OR2 s 0 4 0 1 ~4305~1
- 8 - B 27 OR2 s 0 4 0 1 ~4311~1
- 6 - B 27 OR2 s 0 4 0 1 ~4317~1
- 1 - F 36 OR2 s 0 4 0 2 ~4335~1
- 3 - F 36 OR2 s 0 4 0 1 ~4335~2
- 4 - F 28 OR2 s 0 2 0 14 ~4371~1
- 6 - F 22 AND2 s ! 0 4 0 7 ~4371~2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\ccdproject\ccdcontrol.rpt
ccdcontrol
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 12/144( 8%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 41/144( 28%) 6/ 72( 8%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 8/144( 5%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 66/144( 45%) 2/ 72( 2%) 4/ 72( 5%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\ccdproject\ccdcontrol.rpt
ccdcontrol
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 80 clk
INPUT 1 adreset
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