ccdcontrol.tan.rpt

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

    Info: Processing started: Wed Jun 11 21:47:14 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ccdcontrol -c ccdcontrol
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "adreset" is an undefined clock
Info: Clock "clk" has Internal fmax of 59.95 MHz between source register "readcnt[0]" and destination register "srgcyc[6]" (period= 16.681 ns)
    Info: + Longest register to register delay is 15.972 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N4; Fanout = 3; REG Node = 'readcnt[0]'
        Info: 2: + IC(1.296 ns) + CELL(0.747 ns) = 2.043 ns; Loc. = LC_X6_Y1_N0; Fanout = 2; COMB Node = 'Add2~397'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.166 ns; Loc. = LC_X6_Y1_N1; Fanout = 2; COMB Node = 'Add2~395'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.289 ns; Loc. = LC_X6_Y1_N2; Fanout = 2; COMB Node = 'Add2~393'
        Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.412 ns; Loc. = LC_X6_Y1_N3; Fanout = 2; COMB Node = 'Add2~389'
        Info: 6: + IC(0.000 ns) + CELL(0.261 ns) = 2.673 ns; Loc. = LC_X6_Y1_N4; Fanout = 5; COMB Node = 'Add2~391'
        Info: 7: + IC(0.000 ns) + CELL(0.975 ns) = 3.648 ns; Loc. = LC_X6_Y1_N8; Fanout = 6; COMB Node = 'Add2~400'
        Info: 8: + IC(1.262 ns) + CELL(0.740 ns) = 5.650 ns; Loc. = LC_X5_Y1_N6; Fanout = 8; COMB Node = 'readcnt[0]~1225'
        Info: 9: + IC(2.054 ns) + CELL(0.511 ns) = 8.215 ns; Loc. = LC_X6_Y2_N5; Fanout = 3; COMB Node = 'LessThan6~190'
        Info: 10: + IC(1.960 ns) + CELL(0.200 ns) = 10.375 ns; Loc. = LC_X6_Y2_N1; Fanout = 5; COMB Node = 'srgcyc~515'
        Info: 11: + IC(0.714 ns) + CELL(0.200 ns) = 11.289 ns; Loc. = LC_X6_Y2_N8; Fanout = 4; COMB Node = 'srgcyc~516'
        Info: 12: + IC(0.724 ns) + CELL(0.200 ns) = 12.213 ns; Loc. = LC_X6_Y2_N0; Fanout = 4; COMB Node = 'srgcyc~517'
        Info: 13: + IC(1.800 ns) + CELL(0.200 ns) = 14.213 ns; Loc. = LC_X6_Y3_N0; Fanout = 2; COMB Node = 'srgcyc~527'
        Info: 14: + IC(1.168 ns) + CELL(0.591 ns) = 15.972 ns; Loc. = LC_X6_Y3_N6; Fanout = 3; REG Node = 'srgcyc[6]'
        Info: Total cell delay = 4.994 ns ( 31.27 % )
        Info: Total interconnect delay = 10.978 ns ( 68.73 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y3_N6; Fanout = 3; REG Node = 'srgcyc[6]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y1_N4; Fanout = 3; REG Node = 'readcnt[0]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: No valid register-to-register data paths exist for clock "adreset"
Info: tsu for register "srg~reg0" (data pin = "reset", clock pin = "clk") is 3.750 ns
    Info: + Longest pin to register delay is 6.765 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 43; PIN Node = 'reset'
        Info: 2: + IC(2.489 ns) + CELL(0.740 ns) = 4.392 ns; Loc. = LC_X5_Y3_N1; Fanout = 3; COMB Node = 'srg~542'
        Info: 3: + IC(0.737 ns) + CELL(0.740 ns) = 5.869 ns; Loc. = LC_X5_Y3_N3; Fanout = 1; COMB Node = 'srg~548'
        Info: 4: + IC(0.305 ns) + CELL(0.591 ns) = 6.765 ns; Loc. = LC_X5_Y3_N4; Fanout = 3; REG Node = 'srg~reg0'
        Info: Total cell delay = 3.234 ns ( 47.80 % )
        Info: Total interconnect delay = 3.531 ns ( 52.20 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N4; Fanout = 3; REG Node = 'srg~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
Info: tco from clock "clk" to destination pin "abg[0]" through register "abg[0]~reg0" is 8.130 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N5; Fanout = 1; REG Node = 'abg[0]~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.406 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N5; Fanout = 1; REG Node = 'abg[0]~reg0'
        Info: 2: + IC(2.084 ns) + CELL(2.322 ns) = 4.406 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'abg[0]'
        Info: Total cell delay = 2.322 ns ( 52.70 % )
        Info: Total interconnect delay = 2.084 ns ( 47.30 % )
Info: th for register "iag~reg0" (data pin = "reset", clock pin = "clk") is -2.159 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 74; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N6; Fanout = 2; REG Node = 'iag~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.728 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 43; PIN Node = 'reset'
        Info: 2: + IC(2.489 ns) + CELL(0.740 ns) = 4.392 ns; Loc. = LC_X5_Y3_N1; Fanout = 3; COMB Node = 'srg~542'
        Info: 3: + IC(0.745 ns) + CELL(0.591 ns) = 5.728 ns; Loc. = LC_X5_Y3_N6; Fanout = 2; REG Node = 'iag~reg0'
        Info: Total cell delay = 2.494 ns ( 43.54 % )
        Info: Total interconnect delay = 3.234 ns ( 56.46 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 126 megabytes of memory during processing
    Info: Processing ended: Wed Jun 11 21:47:17 2008
    Info: Elapsed time: 00:00:03