ccdcontrol.map.rpt

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                        ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
; ccdcontrol.vhd                   ; yes             ; Other     ; E:/ccdproject/ccdcontrol.vhd ;
+----------------------------------+-----------------+-----------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 174   ;
;     -- Combinational with no register       ; 99    ;
;     -- Register only                        ; 4     ;
;     -- Combinational with a register        ; 71    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 74    ;
;     -- 3 input functions                    ; 29    ;
;     -- 2 input functions                    ; 63    ;
;     -- 1 input functions                    ; 3     ;
;     -- 0 input functions                    ; 1     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 137   ;
;     -- arithmetic mode                      ; 37    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 41    ;
;                                             ;       ;
; Total registers                             ; 75    ;
; Total logic cells in carry chains           ; 42    ;
; I/O pins                                    ; 8     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 74    ;
; Total fan-out                               ; 694   ;
; Average fan-out                             ; 3.81  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |ccdcontrol                ; 174 (174)   ; 75           ; 0          ; 8    ; 0            ; 99 (99)      ; 4 (4)             ; 71 (71)          ; 42 (42)         ; 0 (0)      ; |ccdcontrol         ; work         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 75    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 41    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 57    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |ccdcontrol|srgad[1]       ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |ccdcontrol|abg[0]~reg0    ;
; 7:1                ; 10 bits   ; 40 LEs        ; 10 LEs               ; 30 LEs                 ; Yes        ; |ccdcontrol|readcnt[0]     ;
; 10:1               ; 4 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |ccdcontrol|cnt[3]         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Jun 11 21:46:53 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ccdcontrol -c ccdcontrol
Warning: Using design file ccdcontrol.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ccdcontrol-ccd
    Info: Found entity 1: ccdcontrol
Info: Elaborating entity "ccdcontrol" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at ccdcontrol.vhd(14): inferring latch(es) for signal or variable "ccden", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "ccden" at ccdcontrol.vhd(22)
Info: Implemented 182 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 5 output pins
    Info: Implemented 174 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 171 megabytes of memory during processing
    Info: Processing ended: Wed Jun 11 21:46:59 2008
    Info: Elapsed time: 00:00:06