fifo.tan.qmsg

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

{ "Info" "ITDB_TSU_RESULT" "pr\[2\] clr rdclock 2.758 ns register " "Info: tsu for register \"pr\[2\]\" (data pin = \"clr\", clock pin = \"rdclock\") is 2.758 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.165 ns + Longest pin register " "Info: + Longest pin to register delay is 5.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.817 ns) 0.817 ns clr 1 PIN PIN_U7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.817 ns) = 0.817 ns; Loc. = PIN_U7; Fanout = 4; PIN Node = 'clr'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.815 ns) + CELL(0.378 ns) 5.010 ns pr\[2\]~150 2 COMB LCCOMB_X37_Y3_N14 1 " "Info: 2: + IC(3.815 ns) + CELL(0.378 ns) = 5.010 ns; Loc. = LCCOMB_X37_Y3_N14; Fanout = 1; COMB Node = 'pr\[2\]~150'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.193 ns" { clr pr[2]~150 } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.165 ns pr\[2\] 3 REG LCFF_X37_Y3_N15 3 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.165 ns; Loc. = LCFF_X37_Y3_N15; Fanout = 3; REG Node = 'pr\[2\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { pr[2]~150 pr[2] } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.350 ns ( 26.14 % ) " "Info: Total cell delay = 1.350 ns ( 26.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.815 ns ( 73.86 % ) " "Info: Total interconnect delay = 3.815 ns ( 73.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.165 ns" { clr pr[2]~150 pr[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.165 ns" { clr clr~combout pr[2]~150 pr[2] } { 0.000ns 0.000ns 3.815ns 0.000ns } { 0.000ns 0.817ns 0.378ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 164 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclock destination 2.497 ns - Shortest register " "Info: - Shortest clock path from clock \"rdclock\" to destination register is 2.497 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns rdclock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'rdclock'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclock } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns rdclock~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'rdclock~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { rdclock rdclock~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.618 ns) 2.497 ns pr\[2\] 3 REG LCFF_X37_Y3_N15 3 " "Info: 3: + IC(0.682 ns) + CELL(0.618 ns) = 2.497 ns; Loc. = LCFF_X37_Y3_N15; Fanout = 3; REG Node = 'pr\[2\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { rdclock~clkctrl pr[2] } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.95 % ) " "Info: Total cell delay = 1.472 ns ( 58.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 41.05 % ) " "Info: Total interconnect delay = 1.025 ns ( 41.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { rdclock rdclock~clkctrl pr[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { rdclock rdclock~combout rdclock~clkctrl pr[2] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.165 ns" { clr pr[2]~150 pr[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.165 ns" { clr clr~combout pr[2]~150 pr[2] } { 0.000ns 0.000ns 3.815ns 0.000ns } { 0.000ns 0.817ns 0.378ns 0.155ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { rdclock rdclock~clkctrl pr[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { rdclock rdclock~combout rdclock~clkctrl pr[2] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "rdclock q\[6\] altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[6\] 5.390 ns memory " "Info: tco from clock \"rdclock\" to destination pin \"q\[6\]\" through memory \"altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[6\]\" is 5.390 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclock source 2.292 ns + Longest memory " "Info: + Longest clock path from clock \"rdclock\" to source memory is 2.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns rdclock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'rdclock'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclock } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns rdclock~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'rdclock~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { rdclock rdclock~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.413 ns) 2.292 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[6\] 3 MEM M512_X36_Y3 1 " "Info: 3: + IC(0.682 ns) + CELL(0.413 ns) = 2.292 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[6\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.095 ns" { rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 55.28 % ) " "Info: Total cell delay = 1.267 ns ( 55.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 44.72 % ) " "Info: Total interconnect delay = 1.025 ns ( 44.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.292 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.292 ns" { rdclock rdclock~combout rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.413ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.140 ns + " "Info: + Micro clock to output delay of source is 0.140 ns" {  } { { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.958 ns + Longest memory pin " "Info: + Longest memory to pin delay is 2.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.065 ns) 0.065 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[6\] 1 MEM M512_X36_Y3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.065 ns) = 0.065 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[6\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.759 ns) + CELL(2.134 ns) 2.958 ns q\[6\] 2 PIN PIN_U5 0 " "Info: 2: + IC(0.759 ns) + CELL(2.134 ns) = 2.958 ns; Loc. = PIN_U5; Fanout = 0; PIN Node = 'q\[6\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.893 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] q[6] } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.199 ns ( 74.34 % ) " "Info: Total cell delay = 2.199 ns ( 74.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.759 ns ( 25.66 % ) " "Info: Total interconnect delay = 0.759 ns ( 25.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.958 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] q[6] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.958 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] q[6] } { 0.000ns 0.759ns } { 0.065ns 2.134ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.292 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.292 ns" { rdclock rdclock~combout rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.413ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.958 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] q[6] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.958 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[6] q[6] } { 0.000ns 0.759ns } { 0.065ns 2.134ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0 data\[0\] wrclock -2.003 ns memory " "Info: th for memory \"altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0\" (data pin = \"data\[0\]\", clock pin = \"wrclock\") is -2.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclock destination 2.348 ns + Longest memory " "Info: + Longest clock path from clock \"wrclock\" to destination memory is 2.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns wrclock 1 CLK PIN_M21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'wrclock'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrclock } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.207 ns wrclock~clkctrl 2 COMB CLKCTRL_G1 20 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 20; COMB Node = 'wrclock~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { wrclock wrclock~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.459 ns) 2.348 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0 3 MEM M512_X36_Y3 1 " "Info: 3: + IC(0.682 ns) + CELL(0.459 ns) = 2.348 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.323 ns ( 56.35 % ) " "Info: Total cell delay = 1.323 ns ( 56.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 43.65 % ) " "Info: Total interconnect delay = 1.025 ns ( 43.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { wrclock wrclock~combout wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.864ns 0.000ns 0.459ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.203 ns + " "Info: + Micro hold delay of destination is 0.203 ns" {  } { { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.554 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 4.554 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.780 ns) 0.780 ns data\[0\] 1 PIN PIN_R8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_R8; Fanout = 1; PIN Node = 'data\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[0] } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.640 ns) + CELL(0.134 ns) 4.554 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0 2 MEM M512_X36_Y3 1 " "Info: 2: + IC(3.640 ns) + CELL(0.134 ns) = 4.554 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.774 ns" { data[0] altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.914 ns ( 20.07 % ) " "Info: Total cell delay = 0.914 ns ( 20.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.640 ns ( 79.93 % ) " "Info: Total interconnect delay = 3.640 ns ( 79.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.554 ns" { data[0] altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.554 ns" { data[0] data[0]~combout altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 3.640ns } { 0.000ns 0.780ns 0.134ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { wrclock wrclock~combout wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.864ns 0.000ns 0.459ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.554 ns" { data[0] altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.554 ns" { data[0] data[0]~combout altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 3.640ns } { 0.000ns 0.780ns 0.134ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}