fifo.tan.qmsg

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "rdclock " "Info: Assuming node \"rdclock\" is an undefined clock" {  } { { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 48 -1 0 } } { "d:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "rdclock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wrclock " "Info: Assuming node \"wrclock\" is an undefined clock" {  } { { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 50 -1 0 } } { "d:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "wrclock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "rdclock memory memory altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~portb_address_reg0 altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[0\] 500.0 MHz Internal " "Info: Clock \"rdclock\" Internal fmax is restricted to 500.0 MHz between source memory \"altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~portb_address_reg0\" and destination memory \"altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.0 ns 1.0 ns 2.0 ns " "Info: fmax restricted to Clock High delay (1.0 ns) plus Clock Low delay (1.0 ns) : restricted to 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.720 ns + Longest memory memory " "Info: + Longest memory to memory delay is 1.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M512_X36_Y3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X36_Y3; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.720 ns) 1.720 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[0\] 2 MEM M512_X36_Y3 1 " "Info: 2: + IC(0.000 ns) + CELL(1.720 ns) = 1.720 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.720 ns ( 100.00 % ) " "Info: Total cell delay = 1.720 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } { 0.000ns 0.000ns } { 0.000ns 1.720ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.058 ns - Smallest " "Info: - Smallest clock skew is -0.058 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclock destination 2.292 ns + Shortest memory " "Info: + Shortest clock path from clock \"rdclock\" to destination memory is 2.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns rdclock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'rdclock'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclock } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns rdclock~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'rdclock~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { rdclock rdclock~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.413 ns) 2.292 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[0\] 3 MEM M512_X36_Y3 1 " "Info: 3: + IC(0.682 ns) + CELL(0.413 ns) = 2.292 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|q_b\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.095 ns" { rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 55.28 % ) " "Info: Total cell delay = 1.267 ns ( 55.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 44.72 % ) " "Info: Total interconnect delay = 1.025 ns ( 44.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.292 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.292 ns" { rdclock rdclock~combout rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.413ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclock source 2.350 ns - Longest memory " "Info: - Longest clock path from clock \"rdclock\" to source memory is 2.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns rdclock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'rdclock'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclock } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns rdclock~clkctrl 2 COMB CLKCTRL_G3 16 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'rdclock~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { rdclock rdclock~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.471 ns) 2.350 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M512_X36_Y3 8 " "Info: 3: + IC(0.682 ns) + CELL(0.471 ns) = 2.350 ns; Loc. = M512_X36_Y3; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.153 ns" { rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.325 ns ( 56.38 % ) " "Info: Total cell delay = 1.325 ns ( 56.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 43.62 % ) " "Info: Total interconnect delay = 1.025 ns ( 43.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.350 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.350 ns" { rdclock rdclock~combout rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.471ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.292 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.292 ns" { rdclock rdclock~combout rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.413ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.350 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.350 ns" { rdclock rdclock~combout rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.471ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.140 ns + " "Info: + Micro clock to output delay of source is 0.140 ns" {  } { { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.022 ns + " "Info: + Micro setup delay of destination is 0.022 ns" {  } { { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } { 0.000ns 0.000ns } { 0.000ns 1.720ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.292 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.292 ns" { rdclock rdclock~combout rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.413ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.350 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.350 ns" { rdclock rdclock~combout rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.471ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|q_b[0] } { 0.000ns } { 0.065ns } "" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 43 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "wrclock memory memory altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0 altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_memory_reg0 500.0 MHz Internal " "Info: Clock \"wrclock\" Internal fmax is restricted to 500.0 MHz between source memory \"altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0\" and destination memory \"altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_memory_reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.0 ns 1.0 ns 2.0 ns " "Info: fmax restricted to Clock High delay (1.0 ns) plus Clock Low delay (1.0 ns) : restricted to 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.720 ns + Longest memory memory " "Info: + Longest memory to memory delay is 1.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0 1 MEM M512_X36_Y3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.720 ns) 1.720 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_memory_reg0 2 MEM M512_X36_Y3 0 " "Info: 2: + IC(0.000 ns) + CELL(1.720 ns) = 1.720 ns; Loc. = M512_X36_Y3; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.720 ns ( 100.00 % ) " "Info: Total cell delay = 1.720 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 1.720ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.046 ns - Smallest " "Info: - Smallest clock skew is -0.046 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclock destination 2.302 ns + Shortest memory " "Info: + Shortest clock path from clock \"wrclock\" to destination memory is 2.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns wrclock 1 CLK PIN_M21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'wrclock'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrclock } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.207 ns wrclock~clkctrl 2 COMB CLKCTRL_G1 20 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 20; COMB Node = 'wrclock~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { wrclock wrclock~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.413 ns) 2.302 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_memory_reg0 3 MEM M512_X36_Y3 0 " "Info: 3: + IC(0.682 ns) + CELL(0.413 ns) = 2.302 ns; Loc. = M512_X36_Y3; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.095 ns" { wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.277 ns ( 55.47 % ) " "Info: Total cell delay = 1.277 ns ( 55.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 44.53 % ) " "Info: Total interconnect delay = 1.025 ns ( 44.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.302 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.302 ns" { wrclock wrclock~combout wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.864ns 0.000ns 0.413ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclock source 2.348 ns - Longest memory " "Info: - Longest clock path from clock \"wrclock\" to source memory is 2.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns wrclock 1 CLK PIN_M21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'wrclock'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrclock } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.207 ns wrclock~clkctrl 2 COMB CLKCTRL_G1 20 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 20; COMB Node = 'wrclock~clkctrl'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { wrclock wrclock~clkctrl } "NODE_NAME" } } { "fifo.vhd" "" { Text "E:/fifo/fifo.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.459 ns) 2.348 ns altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0 3 MEM M512_X36_Y3 1 " "Info: 3: + IC(0.682 ns) + CELL(0.459 ns) = 2.348 ns; Loc. = M512_X36_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_t6n1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.323 ns ( 56.35 % ) " "Info: Total cell delay = 1.323 ns ( 56.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 43.65 % ) " "Info: Total interconnect delay = 1.025 ns ( 43.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { wrclock wrclock~combout wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.864ns 0.000ns 0.459ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.302 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.302 ns" { wrclock wrclock~combout wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.864ns 0.000ns 0.413ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { wrclock wrclock~combout wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.864ns 0.000ns 0.459ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.140 ns + " "Info: + Micro clock to output delay of source is 0.140 ns" {  } { { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.022 ns + " "Info: + Micro setup delay of destination is 0.022 ns" {  } { { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "1.720 ns" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 1.720ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.302 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.302 ns" { wrclock wrclock~combout wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.864ns 0.000ns 0.413ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { wrclock wrclock~combout wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_datain_reg0 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.864ns 0.000ns 0.459ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { altsyncram:altsyncram_component|altsyncram_t6n1:auto_generated|ram_block1a0~porta_memory_reg0 } {  } {  } "" } } { "db/altsyncram_t6n1.tdf" "" { Text "E:/fifo/db/altsyncram_t6n1.tdf" 46 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}