altsyncram_2kn1.tdf

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

--altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix" LOW_POWER_MODE="AUTO" NUMWORDS_A=16 NUMWORDS_B=16 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=4 WIDTHAD_B=4 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=70
--VERSION_BEGIN 7.1 cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END


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--synthesis_resources = 
SUBDESIGN altsyncram_2kn1
( 
	address_a[3..0]	:	input;
	address_b[3..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	data_a[7..0]	:	input;
	q_b[7..0]	:	output;
	wren_a	:	input;
) 

BEGIN 
	ASSERT (0) 
	REPORT "Cannot use value BYPASS of parameter CLOCK_ENABLE_INPUT_A with device family Stratix in altsyncram megafunction"
	SEVERITY ERROR;
	ASSERT (0) 
	REPORT "Cannot use value BYPASS of parameter CLOCK_ENABLE_INPUT_B with device family Stratix in altsyncram megafunction"
	SEVERITY ERROR;
	ASSERT (0) 
	REPORT "Cannot use value BYPASS of parameter CLOCK_ENABLE_OUTPUT_B with device family Stratix in altsyncram megafunction"
	SEVERITY ERROR;
END;
--ERROR FILE